Floating-Point Performance in FPGAs

I just received an email from my old chum Dave Strenski, who is an application analyst at Cray Inc. (the supercomputer company).

As an aside, did you ever see that Homebrew Cray Supercomputer project, in which a young lad called Chris Fenton replicated the functionality of a Cray 1 supercomputer using a Xilinx Spartan-3E 1600 development board? This little beauty is a 1/10-scale, binary-compatible, cycle-accurate Cray-1 implemented in a single FPGA!

Cray 1 implemented using a Xilinx Spartan-3E 1600 development board.

In the above image, the real Cray 1 is shown on the right, while Chris's version -- which is only a few inches tall -- is displayed on the left. The original Cray ran at 80MHz and could use anywhere up to a whopping 32 megabytes of memory (wow)! Actually, it's easy to laugh now, but we have to remember that this was absolutely the state-of-the-art at the time (by comparison, today you can get an Android cellphone with a 1GHz processor and gigabytes of memory... it's a funny old world).

Chris's version was implemented on a Xilinx Spartan-3E 1600 development board. Chris says that his Cray occupies about 75 percent of the logic resources and consumes all of the on-chip RAM. The result is a spiffy Cray-1A running at about 33MHz with about 4 kilowords of RAM. As Chris says, "Now Computer Engineer Barbie has an appropriate place to sit down!"

But we digress...

As I say, I just heard from Dave Strenski, who tells me that he’s written an update to his original FPGA Floating Point performance article from a couple of years ago. In fact, this is the fourth article in a series:

• Latest FPGAs Show Big Gains in Floating Point Performance
• The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors
• Revaluating FPGAs for 64-bit Floating-Point Calculations
• FPGA Floating Point Performance

As another aside, Dave also plays around with solar power as a hobby, and Google has made a video about his local solar project:

But wait, there’s more, because Dave says that he and his cohorts have invented a free way to read utility meters. Now I'm wondering what he does in his spare time...

All of this does raise an interesting question. Not so long ago, we wouldn’t have dreamed of using floating-point representations in FPGAs, because the power-guzzling result would have been horribly inefficient. Now, with thousands of hard-core multipliers at our disposal, all sorts of tricks and techniques we can employ, and the ability to use programmable fabric to implement algorithms in a massively parallel fashion, FPGAs are finding their way into all sorts of floating-point-intensive applications, such as radar, for example.

So, which numerical formats are you using in your FPGA designs: integer, fixed-point, floating-point, binary coded decimal (BDC), a mixture of these, or some other?