@torki: Great -- thanks for this input -- for my paper I was just trying to give a "feel" for it all -- but it's nice to know I was so close -- and if I ever give a talk about this technology, will all of the info provided by everyone's feedback I will be able to nail the numbers :-)
Hi Max! I like your 'about 1 um'. Looking at the ITRS 2011 BEOL roadmap for MPUs (logic) Table IITC2 year 2012 (22nm node), metal 1 is 58nm thick, the intermediate metal layers (say #2 & #3) are either 115nm or 230nm (if 2X for ASICs), and global metal layers (say #4 & #5) are either 123nm or 492nm (if 4X for ASICs). Then adding it all up we get a range from 518nm to 1502nm; so 1.0+/-0.5um for the 5 layers of metal covers it. You are 'Magnificent'!