Everything we've discussed thus far might fall under the umbrella of "conventional technologies." They are simply evolutionary enhancements to -- and adaptations of -- proven and accepted silicon-based materials and techniques. Other materials, if they came into play, could significantly change the 3D IC landscape.
Take graphene, an allotrope of carbon. It has a structure of one-atom-thick planar sheets formed from carbon atoms packed densely in a honeycomb crystal lattice. In addition to being incredibly strong (measurements have shown a breaking strength 200 times higher than steel), this material is an excellent conductor of electricity. It also has fantastic thermal conductivity -- better than even nanotubes and diamond. Suppose we could lay graphene sheets down layer by layer, patterning each layer with the equivalent of transistors and separating adjacent layers with a few atoms of insulating material. The results could be mind-boggling.
Graphene is an atomic-scale honeycomb lattice made of carbon atoms.
Of course, graphene won't be used in this way in the near future, unless something completely unexpected happens. Also, we should recognize the billions of dollars that have been invested in the silicon-based infrastructure. Fortunately, there are other options closer to home.
Monolithic 3D ICs
Here's a 30,000-foot description of a relatively new approach that seems very promising: the Monolithic 3D IC technology. All the following numbers are approximations and/or rounded values. They are intended only to provide a sense of scale.
We start with a regular wafer ~700μm (0.7mm) thick. The active/device layer (the doped region containing the transistors) is ~20nm thick -- 1/50th of 1μm, which is infinitesimal when compared to the thickness of the wafer as a whole.
We then add the metallization layers as usual. These layers may have different thicknesses, depending on what we want them to do (signal or power, for example). Between each pair of adjacent metal layers, we will need an isolation layer (silicon dioxide or a low-k dielectric layer). We end by growing a final layer of silicon dioxide and polishing the surface of the wafer to be as flat as possible. In fact, the wafer is polished multiple times as the metal/dielectric layer combos are added.
Cross section of a standard wafer with metallization.
To provide something to visualize, and to round things furiously, let's say that we have eight or nine metal layers, and that, adding everything together, the stack of metal and insulating layers is ~1μm thick. This is where things start to get very interesting.
Max Maxfield 7/20/2012 4:58:43 PM User Rank Blogger
I'm basking in the glow...
I'm basking in the glow of a "job well done" -- I find it easy to wrap my brain around thsi stuff -- the tricky part is explaining it in such a way that it's easy to for others to understand -- and I have to say that I am VERY PROUD of my diagrams (I will also mention that I never get tired of hearing nice things about my diagrams :-)
Max Maxfield 7/21/2012 12:06:44 PM User Rank Blogger
Re: I'm basking in the glow...
@Brian C.: Thanks for the kind words. I did technical drawing at high-school, but that was about it. However, I've been using Visio since it first came out, and must have spent hundreds if not thousands of hours creating drawings for books and papers and suchlike -- like everything it gets easier the more you do it -- but it can be tricky trying to get everything into a restricted "canvas" -- which is 480 pixels wide in the case of these blogs.
This has taken a good deal of work on your part, Max, to convey exactly what is going on. The diagrams are wonderful, and I appreciate you mention thicknesses oof various layers as we progress; keeps everything in a size perspective.
Max Maxfield 7/21/2012 3:24:09 PM User Rank Blogger
Re: I'm basking in the glow...
@Bill White: Thanks for the kind words Bill. The thing is that I hate reading technical articles that make all sorts of assumptions as to what I know (because I often don't :-) ...I would rather things were spelled out.
And although most people in the industry know that 700um equates to 0.7mm, and that 1um = 1000nm, it's easy (as a writer) to forget that if you aren't working with this stuff all the time you might forget these relationships. Also, younger folks may not immediately tie these things together, so I do try to spell things out.
Truth to tell, I'm rather "chuffed" (happy) that you noticed -- when I write these columns, I'm never sure if what I'm hoping to achieve actually "comes off" if you know what I mean, so having this sort of feedback really helps.
@Max, great article! I'll hazard a guess that heat dissipation is going to be one of the biggest factors limiting how many layers can be stacked, which may drive even greater investment in power-reduction research.
I'm already amazed by the uA-sipping micros out there based on current technology. For example, I think the "Nook Simple Touch" e-reader achieves it's 2-month battery life by using a TI MSP430 to drive the touch-sensors, allowing the main ARM processor, which does the heavy-lifting, to sleep most of the time. (This is just an educated guess based on a quick snoop inside my Nook).
Max Maxfield 7/21/2012 3:19:01 PM User Rank Blogger
Re: Heat dissipation and power reduction
@rfindley: On the one hand we're talking about strata (by which I mean the hydrogen-silicon-cleaved layer with it's metal and dialectric layers) only ~1um thick, so even if you had say 10 of them you are still talking about a combined thinkness of 0.01mm -- so if you put some sort of heat-removal mechanizm/layer on top that should be effective.
Also I believe you can use the virtical vias as thermal heat exchangers.
But, truth to tell, I really don;t knwo enough about this to comment. One of the things I'm interested in is using single crystal diamond as the main substrate/wafer, but that's probably a column for another day :-)
This issue disappear in true 3D-IC integrated systems where : - 3D floorplanning have been done with optimizations on 3D interconnections and gate resizing. - Thin substrates are used for the tiers (1 to 10u thickness). Thermal resistance decrease significantly. - Integrated heatsink is used to evacuate the heat from the volume to the surface. For instance by using TSVs and micro-bumps attached in the power rails. An efficient global heatsink have to collect the heat from the surface.
Max Maxfield 7/30/2012 9:27:29 AM User Rank Blogger
Re: Thermal could begain to be an issue at higher layer counts
@William: I agree -- heat is always a problem -- it's going to be interesting to see where this goes -- if people start using the technology in earnest then tool development will ramp up also.
My doubts are on the announced 1um metal layers. This is possible only with a 1 metal and oxide layer. For a 5 metal layers process, the total thickness will be around 3um or so.
Hi Max! I like your 'about 1 um'. Looking at the ITRS 2011 BEOL roadmap for MPUs (logic) Table IITC2 year 2012 (22nm node), metal 1 is 58nm thick, the intermediate metal layers (say #2 & #3) are either 115nm or 230nm (if 2X for ASICs), and global metal layers (say #4 & #5) are either 123nm or 492nm (if 4X for ASICs). Then adding it all up we get a range from 518nm to 1502nm; so 1.0+/-0.5um for the 5 layers of metal covers it. You are 'Magnificent'!
At 28nm Mx (1 to 6) stack is about 6 times 180nm (metal and via). So this is indeed 1.08 micron. The mid-thick metal is 400nm (metal and via) The thick metal is 1480nm (metal and via)
Max Maxfield 8/2/2012 6:25:27 AM User Rank Blogger
Re: 1um BEOL thickness ?
@torki: Great -- thanks for this input -- for my paper I was just trying to give a "feel" for it all -- but it's nice to know I was so close -- and if I ever give a talk about this technology, will all of the info provided by everyone's feedback I will be able to nail the numbers :-)
If you ask most people if they can explain how mirrors work, their knee-jerk reaction will be, "Yes, of course!" After reading this blog they may change their minds...
One alternative to parallel interconnect in the form of busses is to use a serial interconnect setup. This typically involves a special transceiver block inside the device.
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