For the longest time after I was first introduced to the concept of FPGAs in general -- and to the way their fundamental programmable fabric was implemented in particular -- I guess I thought this was pretty much the only way to do things.
Now, before we plunge deeper into the fray, it's important to note that I'm not even thinking about things like adding hardcore functions, up to and including processor cores. All I'm talking about here is the fundamental programmable fabric we find in an FPGA. (See: Ask Max: What's Inside a Simple FPGA?)
To be a tad more specific, I'm thinking about the concept of having an array of programmable logic, block "islands" in a "sea" of programmable interconnect, where each programmable block contains a lookup-table (LUT), along with a handful of other digital functions like registers, multiplexers, and so forth.
A representation of fundamental generic FPGA programmable fabric.
Of course, I understood that the nitty-gritty details might vary -- such as the number of registers, the number of LUTs, the size of the LUTs (4-, 5-, 6-, 7-, 8-input) -- but I was under the impression that the underlying fundamental concepts were "set in stone" (or silicon, in this case).
In reality, of course, there are many different ways to achieve almost anything in electronics, so we really should not let ourselves be trapped into thinking that there is only one way to achieve our goals. Just for the fun of it -- before we proceed any further -- take a moment to close your eyes, sit back in your chair, take a deep breath, and see if you can come up with any other architectures or technologies we might employ to create programmable devices.
OK, you can open your eyes now. In fact, a wide variety of different architectures have been proposed over the years, some of which were a little on the "pie in the sky" side of things, while others were really quite clever. One technology that especially caught my eye was the TierFPGA from Tier Logic. Sad to relate, Tier Logic folded in the summer of 2010, but it's still interesting to ponder its technology, because you never know when a variation on something like this may suddenly leap back into the limelight.
Conventional FPGA fabric
Let's start by reminding ourselves what conventional FPGA fabric looks like. For the purposes of these discussions, we will assume SRAM-based FPGAs, which I introduced in an earlier column on configuration cell technologies. One key aspect of this is that both the logical functions and the configuration cells reside in the same layer -- the active layer -- on the top of the silicon, as illustrated below:
Traditional FPGA: Logical functions and configuration cells reside in the same layer.
We don’t need to go into too much detail about this here. Suffice it to say that the main body of the wafer is approximately 700μm (0.7mm) thick; in some cases this may be reduced by back grinding to 200μm (0.2mm) thick. The active layer containing the transistors is in the order of ~20nm thick, where 1μm equals 1,000nm, which means that the active area is incredibly -- almost unbelievable -- thin. On top of the active layer we can have multiple layers of metallization, with adjacent layers being separated by a layer of insulating/dielectric material. If we assume, say, 10 layers of metallization and round things up furiously, all of the metal and insulating layers combined will be on the order of 1μm thick. (You can find out more about all of this in my recent column on Monolithic 3D ICs.)
The point of all of this is that a large proportion of the traditional FPGA die is consumed by the configuration SRAM. This has several implications, not the least of which is the fact that the various logic elements (LUTs, registers, etc.) have to be spread out to make room for the configuration cells, which increases the length of the tracks between those logic elements... which increases the time it takes signals to pass through the tracks... which negatively affects performance. Another consideration is that if we ever decide to convert our FPGA design into an ASIC -- in which all of the logic elements are closer together -- then the timing of our design will change.
So now let's consider how the TierFPGA architecture addresses these problems...
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