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Max Maxfield

Ask Max: Verilog & VHDL, Part 3

Max Maxfield
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Crusty
Crusty
8/10/2012 8:35:12 AM
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Re: Good guide
@Max: Now that is what I like, explaining it the way that an old timer can understand.

Have I got this right "The designer of the TTL circuit boards was in fact the top level HDL block you show?".

I must admit it was mind blowing to see the schematic layout when i synthesized my first switches and leds VHDL, it really rammed home the fact that these chips are blocks of logic waiting to be connected. I think what you have just proved to me is that the logic of the FPGA lends itself to parallel manipulation of multiple bits of data on the same clock cycle.

I think like a lot of beginners coming from the 8 bit micro world will, like me, have difficulty in knowing whats best done by a micro or an FPGA. This will be the real test and some possible cause of lost hair.

I presently have an 8 bit micro project, for a cooks kitchen timer with OLED display and rotary switch input, on the go. So I was thinking that this would be a good thing to try and convert to an all FPGA design?



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Jacek Hanke
Jacek Hanke
8/10/2012 7:19:13 AM
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Re: Do you still see a need for standalone MCUs?
I agree with Paul, cause in the end the choice is always yours. In some projects standalone MCU seems to be fifth wheel, but still in many, many, many projects standalone MCU rulez :)

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Paul Clarke
Paul Clarke
8/10/2012 3:17:41 AM
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Re: Do you still see a need for standalone MCUs?
There is a very hard and defiant YES from me on that one.

I work in a world with no FPGAs and only small MCUs. I use 8bit and 16bit MCU or PICs in all our products. They are very low cost, very low power and do everything we need them to do. They are also very small, one is in a 6 pin package.

The point is that we need both MCUs and FPGAs as they have very different skill sets. My industry is about controls but is still very slow in MCU terms so our chips running on 500kHz clock are more than fast enough, in fact I still have delay loops in the code.

You have seen my posts on the PicoBlaze, its not just about putting a MCU in a FPGA it's about why and when to use them. The lines are getting harder to see with MCUs having CPLD hardware on them and FPGAs with hard MCUs in them. However as the saying goes "The Choice Is Yours!".

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hamster
hamster
8/10/2012 12:46:59 AM
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Re: Their is another big difference that I can't quite nail down....
THere is a logic error in my reset code... nothing unusual there!

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Brian
Brian
8/10/2012 12:20:56 AM
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Do you still see a need for standalone MCUs?
 

@All:

I have one question related to all of this...

Do you still see a need for standalone MCUs?  (Yes, with all of their boring little, sequential op codes :-)  Especially given that FPGAs now have integrated soft/hard cores... Just curious.

Immediate thoughts on standalone MCU advantages that come to mind are reuse, cost and power consumption.  Any others?

 

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Brian
Brian
8/10/2012 12:19:38 AM
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Clears it up...
 

Hi Max,

I agree with jacklsw86, great article!  And, the drawings were very helpful - they make it much easier to 'visualize' the explanations in the text.

Re: "Older programmers often think "subroutine" but say "procedure" and "function"..."

I still think "subroutine" and still say "subroutine" but mean "procedure" and "function" - and, I am definitely not that old :-)

Re: "If you are new to Verilog and VHDL, does this clear up any confusion you may have been having?"

Yuuup!  It was much better than our previous "comment discussions" just saying sequential vs. parallel.

Thanks!

 

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Brian
Brian
8/9/2012 11:42:55 PM
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Re: Their is another big difference that I can't quite nail down....
 

@hamster: this is excellent, thanks!

 

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hamster
hamster
8/9/2012 11:04:48 PM
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Their is another big difference that I can't quite nail down....
For me the big difference is that there is no thread of execution, Jumps do not exist, loops do not exists, only parallel conditional evaluation of expressions and   atomic assigment of all variables at once.

This is very hard to explain to software guys, But here is an analogy that works.

The hardware you design with VHDL is like a  spreadsheet, with each row being you state at a given clock cycle, each formulas are ONLY able to reference constants and cells in the row immediately prior, and the formula for each cell MUST BE exactly the same for all cells in a column.

Each Input variable is also a column, and as it is an input you can put values in it as you go. So if you wanted to average  a list of numbers you will need to list the numbers all in column 'A'.

When put in that context, ask a software guy how to calculate the average they will come to a result surprisingly close to the HDL solution of the same problem:

* column A contains the data set, changing over time

* column b <= previous value for column b + previous value in column a

* column c <=  previous value for column c + 1;

* column d <= previous value for column b / previous value for column c, and is the running average delayed by one cycle.

You then have the issue of what to do with the discontinuties on the top row. You can then introduce the concept of a reset signal...

* column A contains the data set, changing over time

* column b is the reset signal (0 or 1)

* column c <= IF(previous column b = 0, 0, previous value for column c + prevoius value in column a)

* column d <=  IF(previous columm b = 0, 0, previous value for column d + 1)

* column e <= if(previous column d > 0, previous value for column c / previous value for column d, 0)

Once this is done the "#REF" errors that happen when you copy your formulas to row 1 disapper when reset is asserted.

If anybody was going to start with a HDL this would most probably be the most  useful excersise to try, then do exacty the same in HDL...

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jacklsw86
jacklsw86
8/9/2012 9:35:10 PM
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Good guide
Great article, Max.

This should solve all the misconceptions between software and hardware programming. Looking back at myself, I thought all programming languages work similarly (newbie thinking) and that I could write something similar in another programming language. How wrong I was. I kinda feel a bit guilty for writing a software-like IP module for a well known FPGA company (shouldn't expose too much details :))

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