A couple of years ago, I was lucky enough to be introduced to Andreas Olofsson, president and chief architect of Adapteva. This man single-handedly invented a new computer architecture and designed his own system-on-chip (SoC) from the ground up -- including learning how to use all the EDA tools. He then took the device all the way to working silicon and a packaged prototype. That's when things really started to get interesting!
After that introduction, I wrote an article about Andreas and his incredible design. Since then, I must admit that I've occasionally wondered what was going on at Adapteva. Then, out of the blue, Andreas called to bring me up to date, and you will not believe what he told me.
A few years ago, while working on various aspects of digital signal processing, he began to ponder a problem: The processing solutions on the market, though very versatile, were not inherently efficient in terms of floating-point operations per watt. He was targeting really complex floating-point problems that require a massive amount of flops. This includes the obvious suspects: radar, medical imaging, and communications infrastructure tasks like beam forming. But even battery-powered handheld applications increasingly must perform computationally intensive tasks while consuming as little power as possible.
He designed the Epiphany chip, an array of processor cores, each equipped with its own local memory and a single-precision floating-point engine. Everything is designed to offer optimum performance while consuming as little power as possible. The chip is extremely scalable -- the Epiphany-III (implemented at the 65nm node) boasts an array of 16 processors, while the Epiphany-IV (implemented at the 28nm node) features an array of 64 processors.
When operating at peak performance, running at 800MHz, the Epiphany-IV offers 100Gflops of raw computing power while consuming only 2W. At 50Gflops/Watt, the Epiphany-IV is 50 to 100X more efficient than anything else out there.
What does this have to do with us here on All Programmable Planet? The Epiphany was always conceived as operating as a co-processor that would offload the main processor. In addition to memory, early systems featured three main chips -- an MCU, an FPGA, and an Epiphany, where the FPGA was used to interface the MCU to the Epiphany.
And then Xilinx introduced the Zynq All Programmable SoC. This inspired Andreas to develop a personal supercomputer system called the Parallella, which is based on a combination of the Zynq and the Epiphany, as illustrated in the block diagram below.
Block diagram of the Zynq-based Parallella personal supercomputer.
Andreas told me the Parallella platform will be built on the following principles:
- Open access: Absolutely no NDAs or special access are needed. All architecture and SDK documents will be published on the Web as soon as funding is available (more on that later).
- Open-source: The Parallella platform will be based on free open-source development tools and libraries. All board design files will be provided on an open-source basis once the Parallella boards are released.
- Affordability: Hardware and SDK costs have always been a huge barrier for developers looking to develop high-performance applications. The goal is to bring the Parallella high-performance computer cost below $100, making it an affordable platform for all.
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