Do you recall my blog from a couple of weeks ago, when I was going on about a free course on programmable technology I would be giving as part of the EE Times University Program?
Well, the course is being held this week, and it's going great guns, as it were. We just finished part 3 today, and I've been overwhelmed by the number of attendees and the amount of interaction we're seeing in the question-and-answer sessions at the end of each lecture. Quite apart from anything else, everyone seems to be having a lot of fun. (I know I am.)
If you are interested in learning more about programmable technologies, we'd love to see you for parts 4 and 5 on Thursday and Friday. Even if you already know it all, please pass the word (via Twitter, Facebook, LinkedIn, and other channels) to anyone who might be interested. Also, for anyone who missed the earlier sessions, archived versions are available by clicking here.
The remaining sessions are going to be real corkers. In part 4, we'll consider the various ways a design can be loaded into an FPGA, including the mystical realm of dynamic partial reconfiguration. We'll also discuss some of the really clever tools and technologies available for debugging and verifying FPGA designs, along with ways to protect your designs from copying, cloning, overproduction, and other forms of attack.
Last but certainly not least, in part 5, we will look at all sorts of advanced concepts and trends, including high-speed serial interconnect, optical interconnect, programmable analog fabric, 3D All Programmable chip technologies, and tools and techniques for creating radiation-tolerant All Programmable designs.
Don't dilly-dally or shilly-shally. Bounce on over to the registration page, and book your seat for a rollicking roller-coaster ride of fun and frivolity. Only thrill-seekers need apply.