In my recent column about the different application domains that can be targeted by all-programmable FPGAs, SoCs, and 3D ICs, I noted that -- in addition to applications like system integration and ASIC replacement -- all-programmable 3D ICs are also ideal for ASIC prototyping and emulation. (See: When to Use an All-Programmable SoC vs. an FPGA or 3D IC.)
In a related column, I described a great example of a 3D IC-based ASIC prototyping and emulation platform -- the HAPS-70 series of prototyping systems from Synopsys. (See: All Programmable 3D FPGAs Drive State-of-Art Prototyping System.)
Well, I just heard about a new ASIC/ASSP/SoC prototyping system from the guys and gals at S2C Inc. Actually, let's take a step back and remind ourselves that at DAC 2011 the folks from S2C announced that they had developed something they called the TAI Verification Module. This is a prototype verification product that allows user designs in FPGA-based prototypes to be verified with massive and fast testbenchs via a x4 PCIe Gen2 channel to the PC.
The latest announcement from S2C is the addition of its newest prototyping platform, the Quad V7, to its V7 TAI Logic Module series -- a new generation of SoC/ASIC prototyping hardware based on Xilinxís Virtex-7 2000T all-programmable 3D ICs.
S2C Quad 7V2000T TAI Logic Module.
The V7 TAI Logic Module series, S2Cís fifth-generation products, are designed to support prototyping for designs from 20 to 180 million ASIC-equivalent gates, using 1 to 9 Xilinx Virtex-7 2000T devices on a single board. Furthermore, multiple V7 TAI Logic Modules can be stacked or tiled to scale up to meet higher gate capacity requirements.
Times have certainly changed since I designed my first ASIC back in 1980. As I recall, this CMOS device was implemented using a 5μm fabrication process, and it contained only 2,000 equivalent gates (where an equivalent gate is typically taken to be a 2-input NAND). In those days of yore, we designed at the level of gates and registers using hand-drawn "pencil and paper" schematics. We didnít have software logic simulators -- our functional verification process involved you explaining your schematics to other members of the team, and them saying "Yes, that looks like it should work."
Similarly, we didnít have tools like the Static Timing Analysis (STA) that William Murray, my co-blogger here on All Programmable Planet, talked about in his recent column. (See: Statistical Design Methodology for FPGAs.) Instead, we worked out which were the critical paths, and then we added all the delays up by hand (no one I knew could afford an electronic calculator in those days).
If someone had told me back then that ASICs (the terms ASSP and SoC hadnít been coined at that time) would one day contain tens of millions of logic gates, I simply wouldnít have been able to wrap my brain around this concept. Also, I donít think I could have wrapped my brain around the level of sophistication available to us in today's design and verification tools. We certainly do live in exciting times. What about you? Did you ever create designs as gate-level schematics?
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