In my recent column about the different application domains that can be targeted by all-programmable FPGAs, SoCs, and 3D ICs, I noted that -- in addition to applications like system integration and ASIC replacement -- all-programmable 3D ICs are also ideal for ASIC prototyping and emulation. (See: When to Use an All-Programmable SoC vs. an FPGA or 3D IC.)
Well, I just heard about a new ASIC/ASSP/SoC prototyping system from the guys and gals at S2C Inc. Actually, let's take a step back and remind ourselves that at DAC 2011 the folks from S2C announced that they had developed something they called the TAI Verification Module. This is a prototype verification product that allows user designs in FPGA-based prototypes to be verified with massive and fast testbenchs via a x4 PCIe Gen2 channel to the PC.
The latest announcement from S2C is the addition of its newest prototyping platform, the Quad V7, to its V7 TAI Logic Module series -- a new generation of SoC/ASIC prototyping hardware based on Xilinx’s Virtex-7 2000T all-programmable 3D ICs.
S2C Quad 7V2000T TAI Logic Module.
The V7 TAI Logic Module series, S2C’s fifth-generation products, are designed to support prototyping for designs from 20 to 180 million ASIC-equivalent gates, using 1 to 9 Xilinx Virtex-7 2000T devices on a single board. Furthermore, multiple V7 TAI Logic Modules can be stacked or tiled to scale up to meet higher gate capacity requirements.
Times have certainly changed since I designed my first ASIC back in 1980. As I recall, this CMOS device was implemented using a 5μm fabrication process, and it contained only 2,000 equivalent gates (where an equivalent gate is typically taken to be a 2-input NAND). In those days of yore, we designed at the level of gates and registers using hand-drawn "pencil and paper" schematics. We didn’t have software logic simulators -- our functional verification process involved you explaining your schematics to other members of the team, and them saying "Yes, that looks like it should work."
Similarly, we didn’t have tools like the Static Timing Analysis (STA) that William Murray, my co-blogger here on All Programmable Planet, talked about in his recent column. (See: Statistical Design Methodology for FPGAs.) Instead, we worked out which were the critical paths, and then we added all the delays up by hand (no one I knew could afford an electronic calculator in those days).
If someone had told me back then that ASICs (the terms ASSP and SoC hadn’t been coined at that time) would one day contain tens of millions of logic gates, I simply wouldn’t have been able to wrap my brain around this concept. Also, I don’t think I could have wrapped my brain around the level of sophistication available to us in today's design and verification tools. We certainly do live in exciting times. What about you? Did you ever create designs as gate-level schematics?
Re: Old ASICs-- And Masks were cut with Exacto and Rubylith tape
Yeah but we had to pay him to let us work there and at weekends he would come round and screw your pelvis to a cake stand
Then he would kill you, dance on your grave and sing, but you tell that to kids these days and they don't believe you
Max Maxfield 1/22/2013 5:22:47 PM User Rank Blogger
Re: Old ASICs-- And Masks were cut with Exacto and Rubylith tape
@Jezmo: We had to carve the ones and zeros from cheese, and we had to round the edges off the ones so they didn't get stuck in the wire, and we had to walk home in our bare feet while our boss rode on our backs, laughing as he whipped us...
Re: Old ASICs-- And Masks were cut with Exacto and Rubylith tape
After the layout group had done their job, they delivered the layout to us as a massive (for the time) ASCII text file. A '1' meant metal layer 1; a '2' menat metal layer 2; an 'X' indicated a via between metal layers 1 and 2; and so on for the P-type silicon and N-type silicon and so forth. This is the file that we had to ptint out in strips and tape together -- then we compared thsi layout to the original schematics in the ring binder.
Yea luxury
We had to carve the ones and zeros from cheese, and we had to round the edges off the ones so they didn't get stuck in the wire, and we had to walk home in our bare feet while our boss rode on our backs, laughing as he whipped us
Max Maxfield 1/22/2013 11:52:46 AM User Rank Blogger
Re: Old ASICs-- And Masks were cut with Exacto and Rubylith tape
@Karl: In the case of our schematics, we hand-drew them with pencil and paper. Once one's fellow design engineers had agreed that things were as they shoudl be, these hand-drawn schematics went to the drawing office where they were re-drawn using official company stencils (and sharp pencils :-) Ofter that, the schematics were kept in a big ring binder as you say.
When I was talking about taping things to gether, I wasn;t talking about the schematics, I was talking about the layout. And by layout I mean the nitty-gritty metal and gate structures on the surface of the silicon chip. After the layout group had done their job, they delivered the layout to us as a massive (for the time) ASCII text file. A '1' meant metal layer 1; a '2' menat metal layer 2; an 'X' indicated a via between metal layers 1 and 2; and so on for the P-type silicon and N-type silicon and so forth. This is the file that we had to ptint out in strips and tape together -- then we compared thsi layout to the original schematics in the ring binder.
If you ask most people if they can explain how mirrors work, their knee-jerk reaction will be, "Yes, of course!" After reading this blog they may change their minds...
One alternative to parallel interconnect in the form of busses is to use a serial interconnect setup. This typically involves a special transceiver block inside the device.
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