Following my previous articles, I have started to receive questions, comments, and other feedback about the high-level synthesis (HLS) flow. (See: High-Level Synthesis for FPGAs, Where Did the Name High-Level Synthesis (HLS) Come From?, Transaction-Level Synthesis & Micro-Architectures, Transaction-Level Synthesis Gets Graphic, and Resource Allocation & Scheduling for Transaction-Level Synthesis.)
So before I go into more details about mapping and pipelines, I will take a small sidestep to consider the importance of the development flow in general, and how verification fits into the flow in particular.
Now, for those of you who are old enough, I want you to cast your mind back to the dawn of RTL (register transfer level). At that time, almost all verification was performed at the gate level. The EDA companies were trying to persuade the industry that they should perform more verification at the higher level of abstraction, but the industry was reluctant to move.
Why was this? Actually, there were several reasons, including the fact that they didn't trust the tools and there were many issues that could not be detected when simulating the input description. Over time, these issues went away, some of them being addressed by alternative tools such as static timing analysis (STA) that are used to perform static timing verification.
Today, we are at that same point with regard to high-level synthesis. Everyone who has adopted transaction-level synthesis has found that the gains in verification time are perhaps even more significant than the gains in the design flow itself. These gains are expanded when it is realized that the same models used for transaction-level synthesis can also be used for additional purposes, such as a virtual prototype for software development.
Having said this, the changes that happen between the transaction level and RTL are larger than they were between RTL and gates. We are not just talking about timing within a clock, we are talking about timing across clock periods, and at this point in time (no pun intended) we simply do not have all of the verification tools necessary to eliminate RTL verification in its entirety.
What this means is that you cannot ditch your RTL simulator any time soon, but you can make it do less of the heavy lifting. A new flow is emerging and new tools are being developed to tackle the problems. Some of the problems go back to my earlier discussions about the separation of computation and communication, so let me start there. (See: Transaction-Level Synthesis & Micro-Architectures.)
Let's begin by considering the diagram I presented in that column:
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