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Brian Bailey

How Can We Connect Functional Blocks to Each Other?

Brian Bailey
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hash.era
hash.era
12/31/2012 3:25:56 AM
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Re: Bus buffering and recovery/re-try
This is the most easiest out of the models so far. If any help needed please let me know. Glad to help anyone out.

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Brian Bailey
Brian Bailey
12/11/2012 10:41:51 AM
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Re: Calculating sped of execution requirements.
@Karl - if TLS/HLS is the most complex notion ever, then I thiunk it is testament to the complexity of making decisions at that level. IN my view the tools are nothing more than allowing some automation of solution generation after the designer has made all of the choices. The tool can perform analysis that will help with decision making, but in the end the tough choices are all made by the engineer.

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Karl
Karl
12/10/2012 4:33:05 PM
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Re: Calculating sped of execution requirements.
@Brian:  Maybe they assumed that "synchronous" meant Dff's as it does for FPGAs.  That means setup and hold times as well as clock skew have to be considered.

Latches allow data to flush through when the clock is high so back to back latches only have to have non-overlapping clocks so clock skew is the big factor so long as the correct data has flushed through the first latch and is stable to flush through the second latch.

Now the focus can be at the cycle level and generating the correct signals during each cycle.  Static timing analysis then is primarily concerned about long paths.

And people are buying into C to silicon and TLS/HLS which have to be top on the list of most complex notions ever. 

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Karl
Karl
12/10/2012 3:38:13 PM
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Re: Bus buffering and recovery/re-try
@Jezmo:  My preference is ping-pong buffering because of fixed length transfers.  Of course some data is variable length, then FIFO is appealing.  But only the last transfer would have to be variable length and that should be pretty straightforward.

I choose ping-pong in the end due to perceived simplicity.  We did have to add a bus line to request suspension of block transfers in order to handle non-buffered peripherals.  The system did work but was not a real hot seller.

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JezmoSSL
JezmoSSL
12/10/2012 3:03:50 PM
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Re: Bus buffering and recovery/re-try
The one thing you have to be careful with is cypress have stopped publishing functional models of their newer FIFOs, so as i did you end up trying to reverse engineering some exceptionally complex parts if you want to model them.

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Karl
Karl
12/10/2012 2:37:16 PM
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Re: Bus buffering and recovery/re-try
@Jezmo:  Does the receiver have a checkpoint/marker to know that it is a retry and write over the previous partial transfer?  Oh, I see -- it picks up at the point of the last successful transfer because of not detecting completion or else gets an "oops" signal . . . may just wait to resume.

And if the receiver fell behind it could signal a retry request.  Tricky, but if carefully implemented . . .

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JezmoSSL
JezmoSSL
12/10/2012 2:14:10 PM
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Re: Bus buffering and recovery/re-try
One of the things you get with cypress FIFOs which I haven't seen in programable logic although it would be doable is you can set a resend marker, so you can effectively mark a block of data within the FIFOS, and cause the FiFO to resend that data, which is very useful, as it is effectively a retry buffer.

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Karl
Karl
12/10/2012 11:35:53 AM
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Bus buffering and recovery/re-try
The primary factor is the time interval that each method provides to smooth out the data transfer.  Given that there will always be cases when peak traffic will exceed the bus/(interface?) capability that means the system needs to handle a missed transfer gracefully.  That means it must be detected and some action taken to mitigate the impact, probably a re-try.

As an example a hard disk data is divided into sectors of equal size.  Each rotation brings each sector under the head where it can be read.  Ping-pong buffers each the size of a sector will either transfer the sectors data or wait one rotation time when the transfer can be retried.  Packet switching could use buffers the size of a packet and a dropped packet would then be re-sent for recovery.

FIFOs that only hold a portion of the data would need to make sure that partial transfers were not used and to re-transfer the data including the part that was successfully transferred because partial transfers are too difficult.

The 2 port rams have options such as independent clocks, different port widths, etc. that provide a lot of flexibility for buffering.

 

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JezmoSSL
JezmoSSL
12/9/2012 3:41:41 AM
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Re: Calculating sped of execution requirements.
No I dont think out of order completion is something which is going to cause problems but its just an example of what the AXI interface is capable of, it is quite powerful and the point I make in my next blog is that you only have to know one protocol in order to implement it in your designs, I think it complements your article quite well and its going to go on to discuss how to get IP blocks communicating with each other and the Cortex_A9 in the case of the zynq.

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Karl
Karl
12/8/2012 10:28:03 AM
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Guru
Re: Calculating sped of execution requirements.
@Brian: Thanks, and I think a cycle simulator should be used with FPGAs.  Static timing analysis came along with cycle simulation so FPGA design is a perfect match. 

Along the same line, modeling an FPGA with OOP classes for registers and memory blocks along with custom classes for logic and data path can easily be done for cycle simulation.  And you really get a lot of debug/monitoring capability for free.

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