Editor's Note: In his previous article, our fearless FPGA newbie, Duane, discussed how he managed to get all four of the light-emitting diodes (LEDs) on his development board flashing furiously. (See: Discovering FPGAs: Flashing the LEDs.)
In this installment, as a lead-up to adding some external LEDs, the daring Duane examines the contents of the UCF (user constraint file) in a little more detail. So now, let's pass the baton back to Duane...
OK, so now I've run the sample code to flash the four LEDs on my development board, and it works. As part of this, I managed to decode the LED pin mapping in the UCF file (that is, the mapping of the signals in the VHDL code to the physical pins on the FPGA that drive the LEDs on the circuit board). Now it's time to get real and actually write some code myself... well, it's almost time...
In my previous column we learned quite a lot about naming conventions and the four LEDs used in the tutorial. Before we proceed further, it will help to know what all of the other lines in the UCF (user constraint file) actually do.
Screenshot of the UCF file used for the LED tutorial.
The four lines starting with "NET LED<…" (line numbers 5, 6, 7, and 8) should look familiar because we discussed them in my previous column, but what about the other lines? We can't just ignore them. Well, we could, but then we'll just get even more confused. First, "NET" is a Xilinx reserved word. It means that, on that line, you are defining a net inside of the chip; that is, you're wiring something up in the silicon.
"CLK_66MHZ" is our word. It's the name we are giving to this net, which will be a clock signal. "LOC" again, is a reserved word assigning a pin. "K15" is that pin on the FPGA. If we make a speed run back to the schematic diagram, we see that pin "K15" is shown on Sheet 5 wired to the PC board schematic net labeled "CLOCK_Y2". On Sheet 6 of the schematic, we can find "CLOCK_Y2" wired to a clock chip with the reference designator "U1". So, the clock chip is generating, of all things, a clock signal (you can only imagine my surprise). That clock signal is wired on the PC board to FPGA pin "K15". Inside the chip, we are connecting that clock signal to an internal net which we have chosen to call "CLK_66MHZ". Presumably the designer picked that name because it's a 66MHz clock signal.
Oh, and something about the double quotes on "CLK_66MHZ" and "K15". You may notice that in the actual file, those two (and one other) are the only constraint identifiers enclosed in quotes. The quotes are optional, but they are recommended by Xilinx. Here, I'm afraid to say that they're a tad confusing, because I've been using quotes when needed for clarity to call out things written in the UCF file (sorry).
The vertical bar is a constraints separator; following that, "IOSTANDARD = LVCMOS33;" is telling us something about this input. If you're curious what this means, return to Sheet 5 of the schematic diagram. The yellow rectangle, on the left-hand side with all of the pins, represents a section of the Xilinx chip. On the left side of that yellow box, you'll see "Bank1 3.3V", which means that all of those pins are 3.3 volt logic pins. Ah ha! So now we know that we're dealing with a low voltage CMOS chip (LVCMOS) that has 3.3 volt inputs and outputs (33). The semicolon is the end-of-line character.
For another example of this, jump to Sheet 7 of the schematic. There, on the left-hand side of the yellow box, you'll see: "Bank 3 1.8V". Those pins are 1.8 volt pins. All of our "NET LED<..." lines have "IOSTANDARD = LVCMOS18", which means a low voltage CMOS chip with 1.8 volt I/O pins. Cool!
On Line 2 of the UCF, "TNM_NET" is a reserved word indicating that the net "CLK_66MHZ" is a timing net; that is, it has a clock signal on it. Now, I need a little help from one of our experts here. The full line is as follows:
So, my question is why is it that the "TNM_NET" has the same name as the "NET"? (Note that reserved words are case-insensitive, so "NET" is the same thing as "Net" and "net".)
On Line 3, reserved word "TIMESPEC" indicates that we are setting the timing specifications. "PERIOD CLK_66MHZ 15000 ps INPUT_JITTER 1000 ps;" is telling us that "CLK_66MHZ" is actually a 66MHz clock (a clock period of 15000 picoseconds equates to a clock frequency of 66MHz).
I'm almost done, which is good because I'm about to collapse in FPGA exhaustion. On Line 10, we have assigned the name "USER_RESET" to one of our inside-of-the-chip nets. "LOC = V4" means that this inside net will connect to pin "V4" on the FPGA. On Sheet 6 of the schematic, we see that pin "V4" is connected to the switch "S5" on the PC board. "IOSTANDARD = LVCMOS33" again tells us that this is a 3.3 volt pin. "PULLDOWN" will attach a pull-down resistor to the net inside the chip (the schematic shows a pull-down resistor on the PC board connected to the switch, but this was not installed, therefore we had to add one inside the chip).
Switch S5 is configured to perform the role of a reset.
The last line: "CONFIG VCCAUX = "3.3" ;" refers to the voltage level on the chip pins "VCCAUX". There are actually 12 pins on the chip that are connected to VCCAUX. On this chip, VCCAUX can be set to either 2.5 volts (the default) or 3.3 volts.
So, I'm now ready to start adding some additional LEDs to the board (using the provided header sockets) and modifying the VHDL code accordingly. But before I do so, have I left any of your questions unanswered?
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