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Duane Benson

Discovering FPGAs: Creating the .BIT File

Duane Benson

Editor's Note: In the previous installment of this mini-series, the daring Duane decided to leave his comfort zone, stop using the command-line mode, and start using the supplied IDE (integrated development environment). (See: Discovering FPGAs: Bringing Up the IDE.)

In this installment, still using the IDE, our intrepid champion walks us through the process of creating the .BIT configuration file. So now, let's hand things back over to Duane...

In my previous blog, we completed the most basic framework of our configuration; now, we're picking up where we left off. My objective in this column is simply to use the IDE to do the same thing we did with our command-line batch files in prior blogs. Before introducing too many variables, I need to be confident that I can use the IDE from start to finish, ending up with my FPGA configured and working.

Learning Verilog (or VHDL) will have to come after this. Based on this objective, I'm not going to go through all of the Verilog code. I'm just going to delete everything in the "ledflash_ISE_ver.v" file and copy and paste the code from our old "ledflash.v" file into here.

So, click anywhere in the Verilog code window, and then type Ctrl-A to select all of the text and -- yes -- delete it! Delete it all! Next, use your favorite text editor to open the "ledflash.v" file we played with in earlier blogs, select all of the text, copy this text, and then paste it into the "ledflash_ISE_ver" window in the ISE. You should now have "endmodule" as line number 56 in the file, as shown below. (Click here to see a larger, more detailed version of this image.)

Creating the .BIT file -- Replacing the Verilog.
Creating the .BIT file -- Replacing the Verilog.

We're well on our way to getting back to exactly where we started, so feel free to take a break and have a soda, coffee, beer, or maybe just a glass of water. But first, use your text editor to open up the other file from our earlier discussions -- the "ledflash.ucf" file. Chapter 5 of the tutorial discusses what we'll be doing next. Again, we're not going to go through all of the tutorial steps here; just the ones needed to get our simple "ledflash" code into the FPGA.

In my last blog, we created a new ".v" source file -- this is the one we just filled with our old code. Today, we're going to create the new .UCF (user constraints file). Open the Project menu in the ISE and select "New Source," which opens up the "New Source Wizard" as shown below. (Click here to see a larger, more detailed version of this image.)

Creating the .BIT file - The New Source Wizard.
Creating the .BIT file – The New Source Wizard.

In the wizard, select "Implementation Constraints File," name it "ledflash_ISE_ver.ucf," and click "Next" to finish the process. Again, we're just trying to get a successful compile / configure here, so I suggest that you do as I am doing, which is to simply copy and paste the contents of our old "ledflash.ucf" file into this new "ledflash_ISE_ver.ucf" file as shown below. (Click here to see a larger, more detailed version of this image.)

Creating the .BIT file - Replacing the .UCF file.
Creating the .BIT file – Replacing the .UCF file.

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JezmoSSL
JezmoSSL
7/28/2012 5:25:50 AM
User Rank Blogger
Re: What to add?
The interesting thing about chipscope is that you can sort of capture signals with it which is a good thing, but the very act of instanciatintg it in your design means that the place and route is changed and if you have a design which is a bit marginal on the timing front then the very act of enabling chipscope can break your design. 

So basically if you do use chip scope you have no gaurentee that what you capture is what happens when you don't use chip scope, which is all very quantum mechanical-ish, the very act of looking at your design breaks it.

Its a far better idea just to bring signals which you need to look at out onto test pins.

 

Altera has a very similar tool which causes the same issues.

 

As far as timing constraints are concerned, if your timing analysis says you meet timing then hurrah!!!!! however if you don't then it may or may not be a bad thing depending on wether you don't meeting timing because you are crossing clock domains in some dodgy manner, or you have some setup and hold issues which may or may not cause problems.

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hamster
hamster
7/28/2012 3:03:35 AM
User Rank Blogger
Re: Timing Analysis & Adding Timing Constraint in UCF
For Xilinx tools, look for the "Static Timing Report" it has all the details - see  http://hamsterworks.co.nz/mediawiki/index.php/Module_7.for more info.

To actually verify if your design really does work at that speed you could run it on progressively faster clocks until it breaks. Because the timing report is based on models of the worst case performance of the device, (e.g. rated temperature limits, voltage limits, on a device that only meets the speed grade) it is quite likely that your design will have quite a lot of headroom.

Also I expect that errors may be very intermittant when you are just under a  flip-flop's setup times...

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maheshhegde
maheshhegde
7/28/2012 12:24:05 AM
User Rank Beginner
Re: Timing Analysis & Adding Timing Constraint in UCF
Dear All,

I have basic idea on UCF file creation, pin assignment. But i don't know to add timing constraints on I/O pins, data path, CLK etc....How to verify it? Wether what i have added constraints is really met in P&R. These are the thing i want to learn.

 

Regards,

Mahesh Hegde

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Adam Taylor
Adam Taylor
7/27/2012 12:31:22 PM
User Rank Blogger
Re: What to add?
Anything I can do to help ?

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Duane Benson
Duane Benson
7/27/2012 12:25:54 PM
User Rank Blogger
Re: What to add?
At the moment, I'm reading up on ChipScop and hope to have something useful to write about it in the next week or so. This is a facinating world, but there's a lot to learn.

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Adam Taylor
Adam Taylor
7/26/2012 3:24:24 PM
User Rank Blogger
Re: Timing Analysis & Adding Timing Constraint in UCF
@maheshhegde, I will be posting quite a bit on UCF as part of my series on the VGA interface. I will ensure I dedicate atleast one blog to the topic 

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Max Maxfield
Max Maxfield
7/26/2012 10:57:38 AM
User Rank Blogger
Re: What to add?
@Hamster: I LOVE the "CheapScope" idea -- something simple to understand and implement that everyone could use...

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Max Maxfield
Max Maxfield
7/26/2012 10:54:26 AM
User Rank Blogger
Re: Timing Analysis & Adding Timing Constraint in UCF
@maheshhegde: As you can see, Duane is writing these blogs describing his learning experiances -- so he will doubtless cover these topics, but it may take some time.


Maybe we can persuade Adam to do a couple of columns on this stuff -- I'll ask him.

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hamster
hamster
7/26/2012 3:40:21 AM
User Rank Blogger
Re: What to add?
Maybe I should write 'cheapscope' - use a block ram to capture signals and then dump them out to the serial port as an ASCII hex string, for capture and analysis on a connected PC. 

Would not be as flexible as chipscope as it needs to be built into your design at prior to implementation, but would be useful when devices don't have JTAG...

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maheshhegde
maheshhegde
7/26/2012 1:53:27 AM
User Rank Beginner
Timing Analysis & Adding Timing Constraint in UCF
Dear All,

Can you please explain on these topics with respect to ISE?

1) Timing Analysis after writing VHDL code

2) Adding timing constraint in UCF file

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