It's been a busy FPGA week. First, of course, I've been continuing the SPI work that I started in my previous blog. Next, I received a new ZedBoard FPGA Development Board in the mail (I will be writing about this little beauty in future columns). And, last but not least, I've been using my primitive FPGA-based mini-logic analyzer to debug an I2C issue in one of my robot boards, and an RS-232 problem on another. For some reason, I2C slaves always seems to be a bit more difficult to set up than their master counterparts, but -- with the help of my Spartan 6 LX9 logic analyzer -- I was finally able to get it going.
I still have a bit of a noise problem in the logic analyzer setup that I'll need to run down, but that didn't get in the way of the problem solving. I also need to build a little level shifter so that I can work with both 3.3 volt and 5 volt signals. But those are all projects for another day.
As you may recall, in my previous blog, I essentially just got the framework for my SPI interface put together. In this week's installment, I want to get the attention of my slave device (my NXP/ARM mbed) by pulling the chip select low, and maybe, just maybe, start the process of clocking data over.
My Spartan FPGA board and NXP/ARM mbed connected together.
Originally, I had been thinking that it would be easier to create a slave in the FPGA, but I subsequently decided that creating the master won't be that much more difficult, but will be a lot more useful in the long run.
In this version, I only have two inputs: a push-button switch and the SPI MISO line. The MISO signal doesn't need de-bounce, so it just gets a two-stage synchronizer module. By comparison, the switch input gets synchronized and de-bounced. I have a couple of suggested de-bounce improvements from comments in one of my earlier blogs that I want to try out at a later date. For the moment, however, the scheme I'm using is mostly like the one described in my De-Bouncing Around blog.
The code for the synchronization and de-bounce module is shown below (click here to see a larger, more detailed version of this image):
As you can see, I've coded this as an independent module to be instantiated in my main code. In lines 33 to 37, we have the two-stage synchronizer code; other than that, this is the same as we've seen before. You can see all of the setup code in the following image (click here to see a larger, more detailed version of this image):
Lines 21 to 42 have the module I/O and the wires and registers I'll need. Lines 44 to 50 creates and buffers the two clocks using DCM: 66 MHz for the main logic and 400KHz for the SPI clock. Lines 55 to 61 divide the 400KHz clock into the 100KHz that the SPI actually needs. Finally, lines 63 to 73 take care of the push button input and the SPI MISO input.
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