As you may recall, I started blogging about my journey into the chaos that is the world of FPGAs back in May of 2012. My original intention had been to learn about, and blog about, both Verilog and VHDL. As things turned out, however, that was a little more of a task than I was up to at the time, so I ended up settling on Verilog.
Now, working with Verilog has certainly been both instructive and fun. On the other hand, since the hardware design language (HDL) world is largely split between Verilog and VHDL, I’ve effectively eliminated half of my potential sources of help. Not knowing VHDL makes it much more difficult to translate help given by non-Verilog users, so I've decided it’s time to go back in time and see what I can do with VHDL.
There are a lot of divided technology camps in the world: Mac vs. PC, Canon vs. Nikon, AMD vs. Intel, Coke vs. Pepsi, etc. People defending a position in one or the other of those sets tend to get very emotional about their point of view. To be honest, I was expecting something similar in the case of Verilog vs. VHDL, but I'm happy to report that I really haven’t seen much evidence of this here on All Programmable Planet. There are some stated pro/cons, but the arguments tend to be more matter-of-fact than emotional. That’s refreshing; however, it doesn’t really make the choice any easier.
Regardless, I’m going back to my Blinky LED in VHDL and -- hopefully -- now that I have a better idea what I'm doing, I’ll be able to progress faster than I did in Verilog. Certainly, I am much less likely to get sucked down the black hole of comparisons with software, as I did with my Verilog work. In the FPGA world, a software mindset is about as effective as stumbling unarmed into Shelob’s lair.
I created a 4-bit counter for my August 6, 2012 blog: Driving a 7-Segment Display. Rather than going completely back to zero, my first VHDL “blinky” will be a version of the four-bit counter I used to drive the 7-segment display. Fortunately, the UCF is the same between VHDL and Verilog, so there’s one less thing I have to re-invent.
Step one is to open the ISE and create a new project: from the ISE file menu, select the very first choice “New Project...” Give your project the name “VHDLcounter” in the “Create New Project” dialog and click “Next.” The “Project Settings” dialog should be set as in the image below. The key is to set your “Preferred Language” to VHDL (click here to see a larger, more detailed version of this image):
Once that’s done, you’ll need to create your VHDL source file, which you do by means of the “Project -> New Source” menu (or just click the "New Source" icon). Select “VHDL Module” from the “Select Source Type” dialog and name it “VHDLcounter.” Following this, you will define the I/O as shown in the image below (click here to see a larger, more detailed version of this image):
Finally, you need to create a “New Source” again, but this time, choose “Implementation Constraints File” and name it “VHDLcounter.” This creates a blank UCF (user constraints file), into which you need to add the following contents (click here to see a larger, more detailed version of this image):
Once you have performed these steps, you will have your UCF and an empty VHDL framework. The Xilinx ISE generated the framework, as you can see in the image below (click here to see a larger, more detailed version of this image):
For comparison, here’s the same framework generated by the ISE in Verilog:
Now, there are a number of new features in the VHDL representation that don’t seem to have a Verilog equivalent. For example, “Library IEEE;” and “use IEEE.STD_LOGIC_1164.ALL;”. So, we use libraries in VHDL. My brain says “libraries = software," but... don’t... go... there (see also the recent VHDL Libraries column that was written by my co-blogger Adam Taylor).
According to the book I have in hand at the moment, Design Recipes for FPGAs by Peter Wilson, VHDL, without library extensions, is quite limited in terms of data types and models; hence, libraries. What we see in lines 20 and 21 of the VHDL code is the name of the library “IEEE” and the element package within that library (“IEEE.STD_LOGIC_1164.ALL”) that we will be loading in this VHDL configuration. The book also notes that the library isn’t specific to VHDL, but is for HDL languages in general. I don’t yet understand the implications of this fact, but I’ll take it without question for the moment.
In my next column, after a bunch more reading, I’ll start putting code into the framework. As best as I can, I’ll compare what I do in VHDL to what I did in Verilog. In the meantime, do any of you seasoned VHDL folks have any advice for a Verilog rookie who is poised to dive headfirst into VHDL?