As you may recall, in my previous column I abandoned all hope -- I mean I abandoned all of my progress in Verilog and jumped back to FPGA day zero to take another look at VHDL. Actually, I haven't quite abandoned Verilog; I've just sent it to its room without dinner and asked its VHDL brother out.
To start with, I've got a stripped-down Verilog counter. I simplified it a bit from last week by removing the "USER_RESET" input. Here it is in all of its minimalist glory (click here to see a larger, more detailed version of this image):
Verilog implementation of a simple counter.
Now, without prior explanation, here's the VHDL equivalent glory (click here to see a larger, more detailed version of this image):
VHDL implementation of a simple counter.
If it was simply a matter of line count, I'd say Verilog is the way to go. But, of course, it's not just a matter of line count; also, you really can't judge anything of substance from an example this small. There's quite a lot more to the question of Verilog versus VHDL, and if the world of experts can't agree which is better, then I'm not going to come to that conclusion anytime soon.
Starting at the top, VHDL lines 1 through 6 opens a pair of libraries and brings in sections of those libraries. Verilog doesn't need that. As I mentioned last week, VHDL doesn't come equipped with a complete set of native types, primitives, models, and such -- instead, these things are defined using libraries. (See also my fellow blogger Adam Taylor's recent column on VHDL Libraries.)
The "std_logic_1164" library contains data types. In this context, I need it for the data types used to declare my "BUFG," "clock_divider," "clk," and "LED" signals. Next, "IEEE.std_logic_unsigned.all" library defines integer math operators. I need this for the "+" operator on line 27. The "UNISIM.vcomponents.all" library contains primitives, such as the clock buffer I'm instantiating. On the Xilinx website, you can find much of this information in its Libraries Guide. The "UNIMACROS" library, which is also listed in the Libraries Guide, may be needed as well, depending on the elements you use.
Verilog, on the other hand, doesn't have a construct equivalent to "library." Much of what you would find in the VHDL libraries is natively accessible in Verilog. For example, my VHDL configuration had to draw from two libraries just to instantiate the clock buffer. In Verilog, I can simply instantiate the clock buffer with the code "BUFG BG (.O(clk), .I(CLK_66MHZ));".
Lines 8, 9, 10, and 11 in the VHDL version define -- what in VHDL is called -- the "entity." The same in Verilog is called a "module" and is defined on lines 3 through 7 in the Verilog example. The declarations are similar, but not equal. In Verilog, the words "input" and "output" define the signal direction. Those signals can be identified as a register ("reg," which is not used in this specific module definition) or as a "wire," which is the default. VHDL identifies the direction using the "in" and "out" keywords along with the libraries that contain the types.
The VHDL "entity" definition covers the input/output (I/O). The VHDL "architecture" declaration holds the internal signal definitions and -- following the "begin" statement -- the HDL circuitry code. Verilog is more free-form. The internal signal definitions and HDL circuitry code are in the module following the I/O declarations. Internal signals and HDL code can be intermixed without a lot of structure. I struggled with this a bit when first learning Verilog, but eventually got to like it that way. On the other hand, I do tend to prefer a more ordered approach.
What about you? If there were a choice in both VHDL and Verilog, would you prefer to keep your signal declarations all in one place, or spread them throughout the HDL code, declaring them near to where they are used?
Re: Keep stirring the pot. Software to hardware conversion comes at a price
@Duane Picking up the logic of some language is one issue. Picking up the vocabulary is quite interrelated and just as important.
I would totally agree with what you said in this reply.
It's so like a learning a second languauge, all the time you consciously have to think in the mother tongue and then interpret to the second language you have trouble communicating.
I am beginning to get a lexicon of words but the vocabulary lacks, as I am still not thinking in my second language yet.
I have started to modify Hamsters PS2 key board code, some success some failure, but it's the second stage in UK101 on an FPGA.
The Address decoder was simple and works on the test bench.
Now I have to find a way to make the key codes from Hamsters logic, act like push button switches on the old UK101 8*8 keyboard matrix input to output.
I am doing it the hard way and not changing the operating code of the UK101
Duane Benson 2/10/2013 3:13:13 PM User Rank Blogger
Re: Now that you've returned to the VHDL fold ...
Mandrews - Thanks for the link. I downloaded VHDL Pacemaker and installed it. A few notes for anyone else that might want to try it out: It does require registration first, but so does everything. What startled me is that it's an installable application (.exe). There's nothing wrong with that, but I always tend to be wary of executable.
It's not compatible with my Windows 7 installation, so I had to install it on the Windows XP virtual machine. I've found that having that VM is pretty handy. This isn't the first applications I've run across that doesn't play well with Win7. Compatibility mode doesn't always help, but the VM solves the problem.
I've just run the tutorial (the tutorial on how to use the tutorial). It seems pretty thorough, but I'll know more once I've run through a bit of the actual VHDL tutorial.
Doulos has a very nice, FREE - aka even nicer - interactive VHDL tutorial called VHDL PaceMaker that's great for breaking into VHDL. Complete with cute little pictures of talking ICs. Includes worthwhile question and answer sessions at the end of each step. They also sell a series of 8 'Golden Books' that are concise, real-world design references. Amazingly helpful. Among them are Golden Books for VHDL and Verilog. I highly recommend them! The people at Doulos have been great to work with, too.
You might enjoy "VHDL for Programmable Logic" by Kevin Skahill of Cypress Semiconductor. Easy entry level book with lots of examples and explanations. Then check out "Essential VHDL - RTL Synthesis Done Right" by Sundar Rajan. This is a book I reference a *lot* along with the VHDL Golden Book while designing.
Welcome back to "real" HDL. :-)
BTW, I do not work for Doulos, nor do I get paid for saying nice things about Doulos or any of the people above - drat.
Duane Benson 2/6/2013 12:11:07 PM User Rank Blogger
Re: Keep stirring the pot. Software to hardware conversion comes at a price
Devel, Jan - Picking up the logic of some language is one issue. Picking up the vocabulary is quite interrelated and just as important. That vocabulary always seems to be more of a challenge for me than it should be. Some times it seems like every text I read has a different take on concepts like the description of what a register is.
I will get it eventually, and I appreciate your insight. It's helping me and will no doubt be helping other newbies out there in APP land.
"I wonder if an optimizing synthesizer will recognize the implicit sensitivity list (it's sensitive to clk_66mhz, reset and clk_divider) and not actually evaluate the statement when there are no events on those signals? "
Devel,
Ooops, I should have said "Even a concurrent assignmentstatement..."
In VHDL, a concurrent assignment statement is equivalent to a sequential assignment statement wrapped in an implied process:
equivalent: process (reset, clk_divider, clk_66mhz) is
begin
if reset = '1' then
clk_divider <= (others => '0');
elsif rising_edge(clk_66mhz) then
clk_divider <= clk_divider + 1;
end if;
end process equivalent;
Just like the equivalent process, the concurrent assignment statement will not execute or be evalutated if there are no events on the signals.
But also just like the equivalent process, the statement will execute again one delta cycle after the clock, due to the event on clk_divider, but clk_divider is not updated because all the conditionals are false. This extra evaluation is what I was referring to by "slowing down simulation performance.
Re: Keep stirring the pot. Software to hardware conversion comes at a price
@Duane "In my mind, a Verilog "register" refers to any form of logic, where "wire" is just an interconnect. So, I'm not using the 7400 series, or inside the CPU definition of register. Just generically to refer to some sort of gate or other active silicon, as used in the Verilog vernacular."
In my mind, a Verilog "reg" is a Verilog thing that I can assign to in two ways (blocking or non-blocking), in a certain context (level-sensitive, edge-triggered, or more general as in a test bench) and that may or may not have a hardware meaning, depending on how it is used.
Note that the HDLs that have survived have mainly been used as Hardware Verification Languages in industry. That is why their semantic power is not limited to "hardware description". Here also one shouldn't be misled by a name.
Max Maxfield 2/5/2013 4:17:19 PM User Rank Blogger
Re: looking good
@aser: Good points -- I think a lot of us had a knee-jerk reaction when we were first exposed to VHDL along the lines of "why did them make it so convoluted" -- but the truth of the matter -- as you say -- is that they designed it to be extremely felexible and adaptable and extendable...
Re: Keep stirring the pot. Software to hardware conversion comes at a price
Duane,
In my mind, a Verilog "register" refers to any form of logic, where "wire" is just an interconnect.
No. See above. Jan and I are trying to disabuse you of this notion.
So, I'm not using the 7400 series, or inside the CPU definition of register. Just generically to refer to some sort of gate or other active silicon, as used in the Verilog vernacular.
the Verilog vernacular is actually a lot worse, since the language includes a lot of primitive and gates that nobody actually uses.
Duane Benson has his SPI interface working. At some point, he'll want to rewrite the Verilog code, but first he wants to get the I2C interface up and running.
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