As you may recall, in my previous column I abandoned all hope -- I mean I abandoned all of my progress in Verilog and jumped back to FPGA day zero to take another look at VHDL. Actually, I haven't quite abandoned Verilog; I've just sent it to its room without dinner and asked its VHDL brother out.
To start with, I've got a stripped-down Verilog counter. I simplified it a bit from last week by removing the "USER_RESET" input. Here it is in all of its minimalist glory (click here to see a larger, more detailed version of this image):
Verilog implementation of a simple counter.
Now, without prior explanation, here's the VHDL equivalent glory (click here to see a larger, more detailed version of this image):
VHDL implementation of a simple counter.
If it was simply a matter of line count, I'd say Verilog is the way to go. But, of course, it's not just a matter of line count; also, you really can't judge anything of substance from an example this small. There's quite a lot more to the question of Verilog versus VHDL, and if the world of experts can't agree which is better, then I'm not going to come to that conclusion anytime soon.
Starting at the top, VHDL lines 1 through 6 opens a pair of libraries and brings in sections of those libraries. Verilog doesn't need that. As I mentioned last week, VHDL doesn't come equipped with a complete set of native types, primitives, models, and such -- instead, these things are defined using libraries. (See also my fellow blogger Adam Taylor's recent column on VHDL Libraries.)
The "std_logic_1164" library contains data types. In this context, I need it for the data types used to declare my "BUFG," "clock_divider," "clk," and "LED" signals. Next, "IEEE.std_logic_unsigned.all" library defines integer math operators. I need this for the "+" operator on line 27. The "UNISIM.vcomponents.all" library contains primitives, such as the clock buffer I'm instantiating. On the Xilinx website, you can find much of this information in its Libraries Guide. The "UNIMACROS" library, which is also listed in the Libraries Guide, may be needed as well, depending on the elements you use.
Verilog, on the other hand, doesn't have a construct equivalent to "library." Much of what you would find in the VHDL libraries is natively accessible in Verilog. For example, my VHDL configuration had to draw from two libraries just to instantiate the clock buffer. In Verilog, I can simply instantiate the clock buffer with the code "BUFG BG (.O(clk), .I(CLK_66MHZ));".
Lines 8, 9, 10, and 11 in the VHDL version define -- what in VHDL is called -- the "entity." The same in Verilog is called a "module" and is defined on lines 3 through 7 in the Verilog example. The declarations are similar, but not equal. In Verilog, the words "input" and "output" define the signal direction. Those signals can be identified as a register ("reg," which is not used in this specific module definition) or as a "wire," which is the default. VHDL identifies the direction using the "in" and "out" keywords along with the libraries that contain the types.
The VHDL "entity" definition covers the input/output (I/O). The VHDL "architecture" declaration holds the internal signal definitions and -- following the "begin" statement -- the HDL circuitry code. Verilog is more free-form. The internal signal definitions and HDL circuitry code are in the module following the I/O declarations. Internal signals and HDL code can be intermixed without a lot of structure. I struggled with this a bit when first learning Verilog, but eventually got to like it that way. On the other hand, I do tend to prefer a more ordered approach.
What about you? If there were a choice in both VHDL and Verilog, would you prefer to keep your signal declarations all in one place, or spread them throughout the HDL code, declaring them near to where they are used?