It's Monday as I wrote these words, and you know what that means... Well, I do. It means that it's feedback time for my prior week's column. I'd rather complete my blogs a little bit sooner, but I get so much good feedback. If I write my new blog before I've seen the feedback from the previous one, then I invariably perpetuate some of my mistakes. Apart from anything else, this is probably not helpful for those trying to learn along with me.
I've been told that the library "IEEE.std_logic_unsigned.all" is not, in fact, a standard library. Thrakkor pointed that out and gave alternates for the library and the code lines dependent on it. After that, devel@latke noted that I don't need to instantiate the clock buffer and that I was using an obsolete bit of code in my frequency divider. And, he also popped right back for another comment to state that I need to initialize my counter in order for the thing to work in the simulator. That last one took me on a quest for the proper way to represent numbers. The basic VHDL syntax is as follows:
In my current test circuit example, this would come out to:
Ooookay... I suppose there's nothing wrong with that, except that, with 27 zeros, it's not unthinkable to imagine missing one out or adding in an extra one. Fortunately, there is another way as follows:
When used as illustrated above, the VHDL keyword "others" will fill the multi-bit signal (which I'm visualizing as a ribbon cable) with zeros, regardless of how many bits are in the array. This raised a few other questions regarding the representation of values in VHDL. In Verilog, I could have represented that value as: "27'b0," but VHDL is different. A single signal value in VHDL is enclosed in single quotes: '0' or '1.' A multi-bit signal is enclosed in double quotes as in "10101010," which is equivalent to "AA" in hexadecimal. Take a look at the following code (click here to see a larger, more detailed version of this image):
Starting at the top, I commented out Line 3 and replaced it with Line 4. Brian gave me an interesting link to a VHDL Math Tricks of the Trade document that contains some detail on the math libraries. This document notes that "numberic_std" is an IEEE standard while "std_logic_unsigned" is a "de facto" industry standard. It recommends the IEEE standard for new designs. Makes sense to me.
I removed Line 16 and replaced it with Line 17. In this case, "clock_divider" is still the signal name, while "unsigned(26 downto 0)" creates an unsigned 27 bit number using the "numeric_std" library. Meanwhile, ":= (others =>'0')" initializes all of the bits to zero. Lines 20 to 24, my original clock buffer instantiation are removed. Line 28 is obsolete syntax, so I replaced it with Line 29. Finally, Line 34 is replaced with Line 35 (phew!).
On Line 35, "LED" is my 4-bit output signal. The four MSBs (most-significant bits) of my counter are routed to the four LED output signals using "clock_divider(26 downto 23)." The "std_logic_vector( )" on this line is a type conversion from "unsigned" to "std_logic_vector." Presumably this is necessary because LED is a "std_logic_vector."
Now it's time to move on to the next step. First, I'll clean up the code by removing all of the unwanted (commented-out) lines. I made a nice little LED Pmod, so I'm going to plug that in for my next column. If you're following along with me, you can continue to use the board LEDs.
All of this provides a perfect segue into my next subject. To date, I've done all of my work in ISE and with physical hardware, but that can only take an FPGA jockey so far. I need to learn how to simulate things in the simulator. Once I get that going, I'll get moving through VHDL world again. A number of options have been mentioned here on All Programmable Planet (APP), but I have ISE, so I'll try out the simulator that's included in ISE. This means I've got to learn about test benches, but -- fortunately -- that's been covered in other blogs here on APP.
Step one is to pull up the User's Guide included with ISE and dig up any tutorials I can find on the Xilinx website. Step two is to stop writing and start reading. With that, I will bid you adieu until next week. I'll see you then -- "Same blog time; Same blog channel."