As you may recall, in my second to last column, which was on the subject of test benches and simulation, I received a comment from Devel@latke.net recommending the book Writing Testbenches: Functional Verification of HDL Models by Janick Bergeron.
I thought I ordered a copy, but instead, a copy of Circuit Design and Simulation with VHDL arrived in the mail. I'm not quite sure how this happened, but this book was one of several listed in a column here on All Programmable Planet (APP) written by my fellow blogger William Murray: Learning FPGAs: What Do Other Engineers Recommend?. This book has a chapter on testbenches, so it will have to do (along with all of the Xilinx materials and the entire Internet, of course).
In my previous column, I created my project and used ISE to create the testbench. First, here's the original VHDL counter code. (Click here to see a larger, more detailed version of this image):
And here's the UCF (user constraints file). The UCF isn't needed for simulation, but it will be required for synthesis, so I created it at the same time. (Click here to see a larger, more detailed version of this image):
My code creates a simple 8-bit counter that displays on some LEDs (light-emitting diodes). To quickly recap the steps:
- Create a project in ISE called "VHDLcountTB"
- Add the two source files "VHDLcounter.vhd" and "VHDLcounter.ucf" to the project
- Create a new source of type "VHDL Test Bench" named "VHDLcountTB"
- Make sure that the radio button for "Simulation," at the top of the design window, is checked and the drop-down below it is set to "Behavioral"
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