FPGAs are all limited by pin count. If you need more pins, then you generally need to move up to a bigger FPGA, unless the device in question offers one of the I/O formats that will support SerDes. Even the lowly LVDS I/O that is common on lower-end FPGAs can handle hundreds of megabits per second, and this allows for a neat trick if one requires more plain old outputs than are available on the chip.
Maxim IC makes LVDS multiplexer and de-multiplexer chips that will allow a few pins of LVDS I/O to clock in and out many pins of LVCMOS logic (see this example). Alternatively, a second, low-cost, FPGA can be used if more inputs are required (don't forget to synchronize the inputs before serializing).
This is how all LCD displays are driven, among other things. Texas Instruments, which recently acquired National Semiconductor, also makes these ICs, but with the merger of the two companies, its Website no longer presents National's old LVDS information in an organized fashion.
If you think about it, even though the bits are coming across serially, the human eye only "samples" a display screen at 10Hz to 20Hz, so the 35MHz data rate is more than fast enough for the Maxim chip to send the data to the display and run its control lines. The bit positions can be used for any applications that use a comparatively slow update rate.
LVDS, like all SerDes, can be a little tricky for the beginner. One must keep the differential signals paired in the board layout -- most CAD (computer-aided design) tools will do this -- and ensure that there is 100 ohms impedance between the two pairs, as well as the recommended impedance to ground (generally 50 ohms to 60 ohms).
This handy application note from Maxim IC explains biasing the LVDS bus so that it will not clock noise while the FPGA is loading its configuration. LVDS can generate EMI (electromagnetic interference), and so proper guidelines need to be followed in order to ensure emission standards are met.
One really key point here is the 100-ohm termination at the end of the LVDS bus right at the receiver. There are two different schemes outlined in the Maxim applications note. The AC-coupled Thévenin method draws less power for those creating portable equipment.
Xilinx provide a number of application notes on LVDS. The code inside the FPGA is just a parallel-in, serial-out (PISO) shift register followed by an LVDS buffer, or LVDS inputs followed by a serial-in, parallel-out (SIPO) shift register.
If one does not need to access all of the outputs continuously, then there are SerDes Cross-Point Switches available from Vitesse that will allow hundreds of these LVDS de-multiplexers to be connected to one FPGA, thereby allowing tens of thousands of digital outputs to be driven every few tenths of a second by a lowly Spartan FPGA, for example.
Have you used any of these LVDS techniques to boost the number of inputs and outputs at your command? If so, please share your experiences here.