Many an engineer has designed an FPGA that has stretched the power supply capability of his board. Alternatively (and perhaps more likely), due to thermal constraints and the fact that leakage current goes up as the board gets hot, he'll have created a design that just does not like to run when the FPGA gets hot. What is one to do about this, given the difficulty of forecasting FPGA power requirements prior to having a completed design?
Well, many FPGA designers are not aware that there is an option to "Synthesize for Low Power" buried in the settings of most of the current synthesis tools. This can take a design that just will not work power-wise or thermal budget-wise and bring it into specification. What are some of the ways that these tools can do this?
During synthesis: The first technique is by means of clock gating -- many of the synthesizer tools are able to see when clocks are not needed and gate them off, cutting the power requirements significantly for those sections of the design.
The next approach is to use some form of "sleep mode." In this case, many of the synthesizers are able to see when a resource such as a multiplier is not in use and to de-select its chip-enable, thereby cutting power.
Post synthesis: Following the main synthesis process, the tool can perform additional gate-level optimizations on the netlist before sending it to place-and-route (P&R). Some of these techniques include:
- Sizing the gate for the load that it presents or is driving.
- Swapping pins on gates so that high frequency output signals are presented with the lowest capacitance routes and input pins.
- Removal of unessential buffers and gates. To quote this whitepaper from Cadence on its tool: "Sometimes timing optimization adds buffers to shield the critical path from a high capacitive load. During timing optimization, the critical path itself could shift. The result is that there are sometimes unnecessary buffers on noncritical paths."
- Improving slew rates on slow rising signals by adding buffers where they will benefit power savings more than they consume.
- Performing logic restructuring. This is a complex process, but the main idea is that portions of the design are replaced with circuits that use less power but that are functionally identical with regard to their outputs.
In practice, later versions of the Xilinx ISE Design Suite were able to take a 250K Gate Spartan 3E from over 300mW to about 225mW when running a 100MHz Ethernet custom MAC application when the "Synthesize for Low Power" option was selected.
Have you had the opportunity to optimize for power, and -- if so -- what have been your experiences?