I remember the first very large FPGA design I attempted. I did not really floorplan the design well; instead, I relied on the synthesis and place-and-route (P&R) engines to "Make the Magic Happen." The design ended up having a 6-bit bus go all the way across the chip to a block RAM and then come back again. As things turned out, the part was large enough that it had enough routing reserves to pull this off. Also, we were lucky that the design only needed to run at 20MHz -- so we managed to get away with it.
Fortunately, Xilinx offers the PlanAhead and PlanAhead Lite floorplanning tools to help alleviate these, and other, issues. Some of the benefits of floorplanning an FPGA design include the following:
- In the process of floorplanning, partitioning between major functional boundaries allows timing compliance to be considered on a block-by-block basis.
- A floorplan targeted at minimizing the trace lengths of high-activity nets can reduce the switching power consumption of a design.
Some of the key points to remember when creating a floorplan are as follows:
- The floorplan is a critical link in the timing closure loop.
- A bad floorplan can dramatically reduce the performance of a design.
- Floorplanning is a good fit for layouts dominated by routing delay or for highly pipelined designs.
- A floorplan usually includes the data path but excludes the control and glue logic.
- A floorplan should consider the FPGA resources such as Block RAM, DSP slices, carry chains, CPU cores, etc.
- High fanout nets may be worth floorplanning.
Keeping all this in mind, let's correct my old design problem on (virtual) paper. First, consider the original design:
The original, un-floorplanned design.
As we see, the dataflow in the original design goes back and forth across the FPGA rather than forging a simple, clean path. Observe that the length of the datapath is close to three times what it needs to be. Also think about the impact on timing and power consumption associated with switching (charging and discharging) these long routes in the FPGA fabric.
Now let's consider the corrected floorplan as illustrated below:
The new, improved floorplanned design.
In this new, improved floorplan, the dataflow path is reduced and does not traverse back and forth across the FPGA. Observe how the routing paths are reduced, which means there is less path length to charge and discharge, thereby improving the timing (increasing performance) and reducing power consumption.
For more information on floorplanning, check out the Xilinx FPGA Floorplanning Guide and visit the Xilinx PlanAhead webpage. Also, some very useful information on floorplanning is to be found in Chapter 15 of Steve Kilts's book, Advanced FPGA Design: Architecture, Implementation, and Optimization.
What are your experiences with floorplanning, pinouts, and issues like the ones I discussed above?