Most FPGA processor cores provided by FPGA vendors are -- to a large extent -- "Black Boxes." One does not get to see inside the box to learn how to design logic. Similarly, many of the IP vendor processor cores come encrypted, or one must execute an NDA (non-disclosure agreement) and Evaluation License, which may be beyond the scope of what one wants to do for casual hobby learning.
The U.C. Riverside VHDL 8051 project is one 8051 core that -- with a little elbow grease -- can be simulated and synthesized with most FPGA vendor tools.
This project does not have the architectural sophistication or extensive tool support associated with the offerings from IP core vendors like Digital Core Design (DCD) or other commercially-available FPGA IP vendor processor cores -- and it does contain a number of limitations to its functionality and performance -- but it will run simple programs for the purposes of teaching oneself the basics of how a CPU core is "done."
The project consists of models of the ALU, internal RAM and ROM, and external RAM, as well as a testbench and support files. A number of sample programs and ROM *.hex images are included in the project. Also, a utility is included that allows you to create a new ROM containing your own program. You will need to compile this C/C++ file (say, "gcc -Wall i8051_mkr.c") and then run it with your *.hex file as a command line argument (e.g., "a.out myfile.hex). This will then produce a corresponding ROM file in VHDL.
The results of simulating 1ms of the included "sort.c" with the 8051 model are shown below (click here to see a larger, more detailed version of this image):
In the above screenshot, the "reset" and "clock" signals are at the top of the waveform display window. The opcode mnemonics are spit out on the "dbg/logic" line at the bottom of the wave window (these are also written to a file). Other 8051 pins may be active depending on the code being executed. The model does not have a full set of peripherals -- such as timers, serial I/O, and analog-to-digital converters (ADCs) -- so it is very basic. It also does not have interrupts coded into the present version. Again, this is a basic educational project, but one can probe down into the model using a simulator and get the gist of how the ALU, ROM, and RAM function.
With further work, one can separate out the non-synthesizable test-bench and the synthesizable model and build an FPGA with the code in it to play with as illustrated in the image below (click here to see a larger, more detailed version of this image):
In order to get the code to synthesize in Synplify, one must bring out the "reset" and "clock" pins to a port on the top of the testbench file, converting it into a top level design file.
For those of you who are experienced with this sort of thing, what were some of the projects you used to learn about FPGA design and tinker with? Some of the other good ones include the LEON SPARC core by Aeroflex and some of the many cores on Open Cores. What are some of your favorites?
And for those of you just starting out, what kinds of questions do you have on processor cores and how simple ones work? Have you tried this core, and did you find any bugs you would care to share, or features you would like to add?