There are many types of ADCs in FPGAs. The most common type is the Successive Approximation ADC, which is used in many of the IP (intellectual property) cores out there. Another type of ADC that's quite simple to implement using an FPGA is the Flash ADC (also known as a "direct conversion ADC"). Flash ADCs are one of the most common and intuitively obvious type of ADCs. They basically work by having a string of equal value resistors with taps for a bank of comparators. This drives some kind of priority encoding circuit followed by a synchronizer for driving clocked digital logic.
Simple FPGA Flash ADC.
In the ADC diagram shown above, the comparator inputs are LVDS (low-voltage differential signaling) signal inputs (see Max's blog on Differential Signaling), with one pin of each differential pair being tied to a common signal input net on the PCB, while the other pins are tied to their respective resistor taps.
This LVDS I/O -- or comparators and single-ended I/O -- drives the priority encoder circuit, which drives the output stage (synchronizers).
Analog considerations beyond the scope of this figure include some type of sample/hold circuit and buffer for the input voltage net on the PCB. These are simple enough to find or make now. The other item is a precision reference and the buffer used to drive the resistive ladder.
Below is the HDL code for the priority encoder and synchronizers. This is a simple prototype created for the purposes of this blog -- it can be refined in many ways, such as making the generics more functional. (Click here to see a larger, more detailed version of this image.):
As can be seen, this is a very simple example with limited capability. Where this technique can be more useful in terms of resolution is to combine this with a Successive Approximation approach and make a semi-flash converter.
Have you used anything like this in your designs? If not, would something like this be useful?
For larger numbers of bits it is possible to follow the ADC with a Calibration Memory
For larger numbers of bits it is possible to follow the ADC output with a calibration memory look up table that is loaded from an area in Config flash or an SPI flash or EEPROM.
These parts should give an 8bit SAR/Flash hybrid ADC a conversion rate of over 10MSPS, and bandwidth in > 30Mhz
One has to recall that most FPGA ADC's are just up to 10-11bits at about 1MSPS and are SAR derivative style ADC's for small silicon area, and a single comparator. This provides a way to combine FLASH with SAR to get more speed for the same # of bits at the added complexity of more I/O and resistors. With the monolithic resistor packs that are matched and precision, virtually all the Non-Linearity and Temperature issues are eliminated for just 1-2 parts. Any fast ADC one puts down will require an amp that will drive a large capacitive load due to the style of ADC construction.
Such ADC is really useful. Its precision is enough, for example, to implement the software defined radio with the proper autoregulated amplification. Even less precision is used in the GPS receiver. The downsampling adds more dynamic range as it was shown in the previous blog.
I have not used such ADC. But I have used such an comparator as the input of the logic analyser. The tuning of the reference voltage helps to estimate the form of the logic signal wave.
Why yes, I have. I've also done the reverse, and used a home-brew DAC.
Where you have to be very careful with this is in the precision of the devices involved. With the inputs (diff rx's), it's not too bad, as they're fairly uniform, but the resistors will kill ya. Even with 0.1% resistors, you will find a considerable percentage error in INL/DNL after only a couple of input "steps," and this is additive accross them all - that is a single imperfect part will affect every input.
From an external viewpoint, they're also pretty slow. All that PCB space makes for a lot of extra trace capacitance, and means that if you want it to have a speed of more than a few kHz, then you need to add high-power drivers that are well-designed to ensure overshoots and undershoots won't damage your digital device. And, the number of resistors required is 2^N, where N is the number of bits. That gets unwieldy, quick.
Internally speaking - you can still buy flash ADCs out there, but you will almost never find one with more than 8 or 9 bits, as the innards start to get really complex around that point. Even from the point of view of the Verilog you presented, it requires a line of code for every possible output. 8 bits would be 255 lines. Ouch! (I guess you could write a little C program to write the lines of code for you, but I have to wonder at what point the syntesizer might start getting angry at you)
For the DAC side, I've used R2R ladders to reproduce 8-bit audio with not horrible results. I've long since gone away from that, though, and started using PWM.
For the ADC, I would probably never consider doing this for more than about 2 or so bits (e.g. 3 states or so), as it immediately becomes more efficient in real estate (both on-chip and off) and code to just plop in a cheap SOIC ADC - and even the cheapest will likely have better results over range and temp.
--Resolution -- The resolution can be increased either by adding resistor taps -- 16=4bit, 32=5bit, ... or by adding a SAR bottom end to the bits. I did not have room or time to show the SAR add-on but may for a later column -- the SAR will slow down the conversion for example for an 8bit converter it may by 6x slower with the SAR's overhead.
I really like the concept. By using this design, you don't have a lot of resolution, but the sample frequency that can be achieved is very, very high.
I've used low resolution flash converters in mixed-signal communication ASIC for decoding Bluetooth signals.
Your idea may be useful in order to decode a high-bitrate modulated signal after the band-base processing. In fact, it could be used for decoding multiple streams/channels in real time.
I also like how it does not have to be a rail-to-rail ADC, or even linear.
Sometimes you might need only to know if it is "higher than ideal", "in the ideal range" or "lower than idea". In which case the ladder needs just three resistors and only four pins are required.
When extreme thermal cycling causes circuit boards and chip packages and the silicon die in the packages to expand and contract at different rates, problems may ensue.
In order to simulate a design we need models that represent the functionality and timing characteristics of our design elements, but the timing aspects of these models may be based on uncertain data.
Designing high-temperature electronics can present many challenges for "down-hole" petroleum equipment, ovens and micro-waves, automotive, medical, aerospace, and other applications.
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