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Paul Clarke

Why PicoBlaze? Introducing This 8-Bit Soft Processor Core

Paul Clarke
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Max Maxfield
Max Maxfield
7/5/2012 3:02:10 PM
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Re: Neat way to offload a main CPU also
@Jason: Just wait until you see what Paul has planning in his coming articles :-)

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Max Maxfield
Max Maxfield
7/5/2012 3:01:09 PM
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Re: Neat way to offload a main CPU also
@Bruce: Hi Bruce -- thanks for taking the time to answer this for us -- Max

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thrakkor
thrakkor
7/5/2012 2:54:26 PM
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I once inherited
I once inherited an FPGA design (xc2v30, V2Pro) that had 3 independent (but related) PB based state machines.  One of them communicated with each of the other 2 (comm interface controllers) as well as other things (pure HDL) in the system (VME, MGTs).

In some instances the PB were well chosen for their intended uses (one or two repetitive operations), but in others, I think were not the best choice and a traditional HDL FSM would have worked better.

I do remember the call/return capability was very useful as well as the internal scratch RAM.  Debug could sometimes be a PITA due to having no internal visibility and being stuck with decoding adrs/data ports.  They simulated well, too.

On the flip side, I've written some monster HDL FSMs that could probably have benefitted from offloading some functionality to one or more PB controllers...  my problem is knowing when/how to balance FSM/MCU within a design.

I would have a preferred an RTL solution, rather than the Xilinx structural design.  I do remember stumbling across a verilog RTL version, but never tried it.

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Jason Teo
Jason Teo
5/31/2012 10:00:30 PM
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Re: Neat way to offload a main CPU also
Hi Bruce - Seem pretty simple, just need an additional step to compile the PicoBlaze program using the assembler into VHDL or Verilog files to use in the routine RTL design flow. Got it. I just got my Spartan 3A starter kit working again with the ISE Webpack 14.1, after leaving it on the shelf for the past 3-4 years. I'll definitely try out the PicoBlaze examples. Thanks for all these information.

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bfienberg
bfienberg
5/31/2012 11:13:34 AM
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Re: Neat way to offload a main CPU also
Hi Jason - Max asked me to look into your question and here's what I found out from the technical experts here at Xilinx.

They tell me that the PicoBlaze macro itself is a single VHDL or Verilog file. When you use the supplied assembler to assemble a PicoBlaze program that you have written (a PSM file) then it will write out a VHDL or Verilog file that defines the Block Memory containing that program. You then have two VHDL or Verilog files that you use in your design and absolutely everything about the processing of those files is completely standard to an HDL/RTL design flow. They say it's that simple and the interface to PicoBlaze is straightforward and obvious so no difficultly connecting it to the things you want to monitor and/or control.

 

The real fun begins once you have configured a physical device with a design containing PicoBlaze. That's when you start using the 'JTAG Loader' utility. In ~10 seconds you can assemble a new or modified program and download it directly into the Block Memory while the rest of your design remains active. This means that you can develop your programs 'on the fly' and that  'first program' only needed to be a placeholder. I can't profess to be a designer, but that sounds pretty cool to me.

 

Once you're happy with your program it just takes one last run through the tools to generate a configuration image (BIT file) that contains your final program because each time you run the assembler it wrote out a new VHDL or Verilog file.

- Bruce

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Max Maxfield
Max Maxfield
5/31/2012 10:08:08 AM
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Display in Times Square
As I mentioned before, I remembered some huge LED display in Times Square that used Xilinx FPGAs and PicoBlaze soft cores. Thsi was circa 2004. I contacted Mike Santarini, Publisher of the Xilinx Xcell Journal magazine, and he gave me a link to the issue containing this story. It's the cover story on Page 10 http://bit.ly/LJCOvU

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Jason Teo
Jason Teo
5/30/2012 9:10:29 PM
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Re: Neat way to offload a main CPU also
Hi Paul,


My curiosity and interest have definitely been kindled. I wonder how easy it is to use the PB compared to the PIC. Plan to set aside some time and get some hands-on with the PB. Look forward to your next article.

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mkr
mkr
5/30/2012 4:18:50 PM
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Re: Neat way to offload a main CPU also
The newer version of PB has ROM for 4k instructions. Quite an improvement.

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Paul Clarke
Paul Clarke
5/30/2012 10:36:43 AM
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Re: Neat way to offload a main CPU also
Hi Jason,

I've looked into the detail of the Verilog as much as the VHDL, but from what I have seen you should be ok with your own RTL blocks. Xilinx have used their own components references so that it builds in a predictable way for the given device. If you download the package and have a look you will find that there is really very little in it and should answer your questions on the Verilog side. However you will see that the picoBlaze is in its own block with sub components like the prom image etc so apart from pulling across signals from lines like the GPIO should be all very self contained.

The build is exactly the same as normal. Only thing that changes is when you want different code then you edit this, compile to a .vhd or .v file and this is included in your Synthesis onwards.

Look out for my next post that covers the building of the core into a project. I'd love to post more often however I have other commitments – but please post questions here or start a board and ask away!

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Duane Benson
Duane Benson
5/30/2012 10:14:35 AM
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Re: Something for Duane?
Some 8-bit machines are pretty scary too. I'm a big fan of PIC processors, but the bank switching necessetated by the odd segmented memory architecture in some of the chips is frightening in assembly language.

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More Blogs from Paul Clarke
Now it's time to look at the memory interface that will supply the information required by our PicoBlaze 8-bit soft processor core.
We've now reached the point where we are ready to start debugging a PicoBlaze-based design using the ISim software simulation tool.
For some reason, my simulation never loads my memory with any contents. Instead, it's left containing undefined ('UUUU...') states. Can you help?
The PicoBlaze does not come with the ability to single step, set breakpoints, and monitor registers and memory, so we need a way to get around these limitations.
As opposed to rebuilding the entire design every time we "tweak" the code we wish to run on the PicoBlaze soft microcontroller core, we can simply use a JTAG tool to load our executable code directly into the FPGA's on-chip memory.
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