I had cause to think more deeply about power consumption recently when I took delivery of a new laptop. It has a processor that runs more 10 percent faster than my old one and has four times the DRAM but burns considerably less power. You couldn't have the old laptop on your lap, because it soon got unbearably hot. The new machine actually works fine as a real laptop.
The same laws of physics apply to processor chips and to FPGAs, so let's look at why semiconductor vendors are so fixated on power consumption.
At this point, we might want to review some (very) simple semiconductor design considerations. The ideal field effect transistor would act like a switch with infinite impedance when it is off and zero resistance when it is conducting. CMOS technology above 100nm gave a good approximation to this ideal. Equally important was the fact that moving from, say, 130nm to 90nm gave a triple benefit from Moore's Law. The packing density doubled (given by the square law 130 x 130/90 x 90 = 2.08), thereby allowing for significant growth in logic capabilities. The selling price halved for a given density, because of the same phenomena.
Finally, the smaller transistors and the thinner metal tracks have lower capacitance, so the dynamic power consumption is reduced (given by the well-known equation P=CV2f, where P is power, C is capacitance, V is the core supply voltage, and f is the clock frequency). It's a classic case where price plus density plus power equals a win/win/win situation.
However, as processes continued to push into the deep submicron realm, things began to change. The core supply voltage had to be reduced to one volt or lower, because the tiny transistors could not withstand higher voltages. This had an unfortunate effect: The gate could not turn the transistor off as hard as before, and each transistor started to leak a few picoamps of current between its source and drain. Though this leakage is small for an individual transistor, it becomes significant in today's high-end FPGAs, which can boast billions of transistors. Thus, the FPGA industry started talking about (and worrying about) quiescent as well as dynamic power.
In just about every case, high power consumption is undesirable for several reasons. It will increase the cost of the power supply, and it may require additional hardware. The heat generated has to be calculated and handled by natural convection or forced air cooling. A high temperature also reduces the reliability of the whole system. For example, the FPGA could be heating up nearby components and affecting their performance. On the FPGA itself, the maximum transistor junction temperature is the key parameter. The power dissipated on the chip heats the transistors and must escape through the package.
I always think of thermal resistance in terms of electrical resistance. This simple analogy relates electrical resistance with thermal resistance, voltage with temperature, and current with heat flow. An electrical resistor generates a voltage across it when a current flows, and a thermal resistance gets hot when heat passes through it. The higher the thermal resistance, the more the temperature rises as the heat flows from the hotter transistor junction to cooler areas.
FPGA vendors quote thermal resistance (Theta-ja) for the path from the transistor junction, through the silicon, and to the surface of the package. A heat sink on the package will lower the thermal resistance for the heat escaping from the package to the air, and a fan can lower it further. The tracks on the PCB also help conduct the heat, and the resulting thermal model can become quite complex.
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