In part 1 of this mini-series, I wrote about some of the causes and issues surrounding power consumption in FPGAs. Now I'd like to look at how customers can get an estimate of what the power consumption will be before writing any detailed code.
Unless you have been living on another planet, you'll know that Altera and Xilinx (this site's sponsor) compete vigorously against each other at every opportunity. As a result of this healthy competition, both claim that their products are the lowest-power or fastest options on every possible occasion. Can they both be correct? Well, yes and no. A quote from Lewis Carroll's Through the Looking Glass would seem appropriate here. "When I use a word, it means just what I choose it to mean -- neither more nor less."
The only really accurate way to get a definitive comparison between technologies is to complete an identical design with both vendors. This is not realistic, but help is at hand.
As I stated in my previous blog, at the 28nm node, Xilinx chose to use the 28nm high-k metal gate (HKMG) technology from TSMC for all of its 7 Series products. The company calls the 28nm HPL, or 28 HPL, a high-performance, low-power process. Based on this, I'd imagine any other process would burn more power and run slower.
Then I read that the Altera Stratix V is using a different TSMC process called 28HP, which it describes as a high-performance process. Even more bemusing is the fact that Altera will build its Cyclone V and Arria V products using TSMC's 28-nm Low-Power (28 LP) process.
Reading the information available from the two companies on the web does not resolve the question of which has the better solution. Altera has a whitepaper that details its choice and includes a graphic to justify the selection of HP for fast devices and LP for power-frugal families. The whitepaper says, "Altera's devices consume the lowest total power of any FPGAs at the 28nm node." So there you have it, at least until we study the list of comparisons on the Xilinx website that compare the power consumption of Artix, Kintex, and Virtex-7 devices with Altera FPGAs. On closer inspection, though, things are not quite so straightforward. For starters, two of the comparisons use an Artix and a Virtex device that Xilinx dropped from its plans a couple of months ago. That's a bit naughty.
The results are derived from the power estimators that both vendors provide. For example, the Xilinx Power Estimator (XPE) is an Excel spreadsheet similar to the Altera PowerPlay Early Power Estimator. Both estimators provide an early approximation for static and dynamic power consumption. You simply choose the device you expect to use -- including the package, speed, and temperature grade -- and select typical or maximum power. (What kind of engineer designs to typical values?)
Next, you add how much logic and memory you expect to use and specify your anticipated clock speeds, along with the average toggle rate. You also include any details about transceivers, clock modules, and general-purpose input/outputs (GPIOs), et voilą -- the answer appears. The number won't be as accurate as the final routed design, but it's a lot better than just trusting to luck. (Click here for a larger version.)
The Xilinx Power Estimator (XPE).
Clearly, there will be many unknowns, but a reasonably accurate estimate early in the design phase can highlight that the device might need cooling with a heat sink or fan, or that a more expensive power supply might be required. It is preferable to identify these possibilities early on, rather than be presented with a nasty surprise near the end of the project.
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