In Part 1 and Part 2 of this mini-series I wrote about the causes of high power consumption in FPGAs and the estimators provided by the vendors. Today I'll look at a novel method that Xilinx has developed for reducing the maximum power consumption.
In my previous column, I discussed the Xilinx Power Estimator, which is an Excel spreadsheet that provides an approximation for the static and dynamic power consumption from a few basic values supplied by the user.
In the past, Xilinx, along with other vendors, has occasionally offered devices screened for lower power. This selection has historically been based on static power consumption and is made during the test phase of the silicon. It relies on a comprehensive characterization of the design, so that the vendor can be confident that the selected devices will meet both the speed parameters and the lower static current specification. Normally the selected devices are slower than the standard devices and require a separate set of speed files and may have a price premium. The selection is allocated a separate part marking that has to be ordered to take advantage of the lower power dissipation. This adds cost for the vendor because it requires additional inventory throughout the supply chain, as well as requiring support in the software and literature.
However, Xilinx has come up with a novel idea, which gives things a new twist. At this point I would suggest that you fasten your seat belts as the ride gets bumpy from here. As you may recall from Part 1 of this mini-series, the core voltage in modern FPGAs has reduced to 1.0 volts or lower. This means that the core voltage is approaching the point where the gate voltage struggles to control the transistors over the normal range of process variations. Of course, the threshold voltage of the transistors in the particular FPGA in the board on your desk might lie anywhere in the process spreads.
When Xilinx characterized the Virtex-7 products, they found the expected spread (similar to a Gaussian distribution) of speed/power performance. The fastest product will be destined for the faster speed grades, but this still leaves a range of devices in the slowest "-1" speed bin. What Xilinx noticed was that, while the entire product met the speed performance when operating at 1.0 volts core voltage, there was a proportion that met the "-1" speed when the core voltage to the logic and memory was set to 0.9 volts. Unsurprisingly, these were also the devices that drew the highest static current at 1.0 volts. Xilinx realized that if it could identify and reduce the static dissipation of the highest leakage devices, then it could lower the worst case number for the entire "-1" speed bin.
Now, here's the clever bit (no pun intended)... rather than create a separate selection bin, Xilinx decided to code these devices in the non-volatile memory on each chip by setting a designated bit high. This is called the Voltage Identification bit (VID bit). All devices can therefore operate satisfactorily at 1.0 volts, but those devices with the VID bit set can also operate perfectly satisfactorily if the voltage is subsequently reduced to 0.9 volts.
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