As I outlined in a previous What's Next blog, I will be talking to some of the visionaries of the programmable industry to get their ideas on 1) Where have we been? 2) What are today's challenges? and 3) Where might we end up in the next several years? This will provide the rest of us with a starting point for our own discussions, thoughts, and prognostications. In five years' time we can look back and see who was the closest (and who was the furthest) from where we actually end up.
Last week I posted some comments from Steve Trimberger, Xilinx Research Labs fellow, in which we mused about "Where have we been?" with regard to programmable fabric. (This might be a good time to remind you that our very own Max Maxfield has been blogging furiously on FPGA fabric. If your knowledge in this area is a little rusty, it might be a good idea to peruse Max's last few columns to brush up on your fabric terminology before proceeding further.) Today's blog covers some of Steve's thoughts with regard to "Todays challenges" and, as usual, I have started a new message board for us to continue the discussion.
The importance of power
Steve says that he sees a couple of key challenges that will require innovative responses in the future. The most important of these appears to be the operating power. As we add more transistors to each generation of FPGAs (Moore's Law continues to apply to FPGAs), the amount of power required goes up. If this power increase isn't mitigated somehow, then it may become the limiting factor with regard to FPGA capacity. Of course, power and performance are related -- if the power requirement becomes too large, then the performance must be scaled back. For example, signal lines that cross much of the chip may require buffers to reduce signal delay. These buffers require extra power. If this is needed on a large number of signals, the overall device power requirement can skyrocket.
From Steve's point of view, power is just one more variable that needs to be balanced with cost, capacity, and features. Having said this, Steve believes that all of the easy power-saving techniques have already been found. Circuit tricks and optimizations have allowed FPGAs to make incremental power savings in each generation. Voltage scaling in particular has helped tremendously, but how much further can we scale? More recently, architecture changes (like those discussed in my previous blog, such as larger lookup tables with more inputs, dedicated logic functions for DSP and arithmetic, better usage of block memory, etc.) have allowed the FPGA fabric to do more with less power. So where can the next round of power innovations come from?
Another key point about power optimization is that it is important to provide designers with easy-to-use tools. It isn't an optimal solution, from Steve's perspective, if the tools require too much specialized knowledge and/or designer intervention in order to control the FPGA's power consumption. The tools should allow the customer to identify goals, levels of importance, and other system-level characteristics, but they should not require the user to operate at the gate level to control power. This looks to be another area for innovation. Creating tools that allow customers to innovate, but that also provide automated control for power optimization (along with the normal capacity and performance goals) may require some additional capabilities that don't currently exist. It all comes down to the right combination of fabric and tools.
Are there other FPGA challenges you think will be important in the next few years? What types of design goals have been difficult for you to achieve with current FPGA devices? Please jump to the FPGA Fabric: What Are Today's Challenges? message board and add your thoughts and comments.