All Programmable Planet - Warren Miller - Low-Power FPGAs: Today's Challenges

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Warren Miller Low-Power FPGAs: Today's Challenges Warren Miller, Independent Consultant, 8/8/2012 Bio Email This Print Comment 4 comments Login 50% 50% As I mentioned in an earlier column, I am currently in the process of talking to some of the visionaries of the programmable industry to get their ideas about: Where have we been? What are today's challenges? What will the future look like? The idea is that this will provide the rest of us with a starting point for our own discussions, thoughts and prognostications. In my previous blog, I talked about the recent history of low power in FPGAs, based on my discussion with Arif Rahman, an IC design architect at Altera. In this column, which is again based on my discussion with Arif, we will consider the challenges we face today. As usual, I have started a new message board for us to continue the discussion. Using the All Programmable Planet message boards is helpful, because we will eventually circle back to this topic (in future interviews or related blog posts), and these message boards will facilitate our picking-up the discussion from where we left off. FPGA customers are increasingly "power aware" If you don't think power is an issue for today's designs, you need look no further than at the recent projections from the Intelligent Energy Europe project. They project that, by 2015, the costs for the operation of servers will exceed the cost of the server hardware! Similar projections have made low power a key requirement for several segments of FPGA customers. Other segments will surely follow suit. Arif explained that, in response to these projections, today's FPGA customers are becoming much more focused on the efficiency of the FPGA -- in particular, on power versus performance. For example, high-speed SerDes are critical high-performance elements in many designs, but customers don't want overall bandwidth to be limited by the FPGA power budget. Thus, metrics like power efficiency (measured in mWatt per Gigabit) of the SerDes channel are now more important than just Gigabits per second. Furthermore, customers are looking for SerDes implementations that can be scaled for lower power per channel when the highest performance data rates are not required. And SerDes channels that can be completely turned off, when not needed, can reduce power even more. Next page > Page 1 / 2 Next > Email This Print Comment comments Newest First \| Oldest First \| Threaded View [close this box] Karl 8/9/2012 10:32:08 AM User Rank Guru - easily done with a 'simple' programmable... A simple programmable building block can be done by using memory blocks and LUTs for combinational logic. The size and width are determined by the function to be performed and the data width required. Variables and constants are all the same width. The memories address regs and data cells are used instead of registers and the memories are cascaded using phase shifted clocks. and dual port mode is used for high bandwidth. Some memories are read only, some seldom written and only a couple are written each cycle. Programmability is a matter of loading memory and power consumption is a matter of the memory blocks and interconnect. Reply Post Message Messages List Start a Board Login 50% 50% Warren Miller 8/8/2012 1:21:19 PM User Rank Blogger Re: Flash-based FPGAs @halherta- Don't be surprised if we get to see the MicroSemi take on low power in a future blog. As far as less souped-up, in many programmable applications that require low power you don't need alot of special features. If the low power programmable is used to 'wake' the rest of the system you might just be looking for a specific address on a serial protocol, a sequence of keypad presses or activity on a sensor (out of range, in range, or "Danger Will Robinson")- easily done with a 'simple' programmable... Reply Post Message Messages List Start a Board Login 50% 50% halherta 8/8/2012 1:07:35 PM User Rank Beginner Flash-based FPGAs Flash-based FPGAs from Actel->MicroSemi are typically low power w.r.t. to SRAM-based FPGAS from Xilinx/Altera. This document compares power dissipation of the Flash-based IGLOO family to the SRAM based Cyclone 3 and Spartan 3 parts. The power savings of the IGLOO family seems to be quite significant over the other SRAM-bsed FPGA families I realize that Flash Based FPGAs from Microsemi might not be as "souped up" as the SRAM based FPGAs from Xilinx/Altera e.g no block RAM, multipliers, DSP blocks e.t.c, but perhaps the general concepts of using Flash-based FPGAs or even having certain portions of the FPGA fabric flash based might significantly reduce the power consumption of FPGAs. Reply Post Message Messages List Start a Board Login 50% 50% Max Maxfield 8/8/2012 12:06:21 PM User Rank Blogger Mind-blowing @Warren: It blows me away that you can do things like introducing tensile strain and compressive strain to speed transistors -- both the fact that it works (mechanical strain speeds electronic switching) and the way in which it's achieved ... who comes upo with this stuff? Reply Post Message Messages List Start a Board Login 50% 50%		More Blogs from Warren Miller A Chess-Playing FPGA: Generate, Propagate & Attack! 3 comments In this blog we consider the attack logic for a single square; this can then be replicated to create the entire 64-square chess board. Implementing SerDes for FPGAs: More Challenges, Part 2 3 comments Now we are ready to consider the equalization, adaptation, and 2D eye scan blocks used in the receiver portion of a high-end FPGA transceiver. A Chess-Playing FPGA: The First Testbench! 14 comments Is the low-level module testbench described here sufficient, or is there a better approach? Should a self-test testbench be used? How important are concepts like portability, ease of understanding, and ability to make modifications? Implementing SerDes for FPGAs: More Challenges 3 comments When traversing serial links with optics or backplanes, high-speed signals are degraded by impairments in the link, such as insertion loss, reflections, crosstalk, and optical dispersion. A Chess-Playing FPGA: Let the Coding Begin! 114 comments Warren has finally started to write some HDL code to implement his chess-playing FPGA, but he's not a professional coder, so he needs our help and advice. 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