As I outlined in an earlier column, I have been talking to some of the visionaries of the programmable industry to get their ideas about where we have been, today's challenges, and how the future will look. The idea is to give the rest of us a starting point for our own discussions, thoughts, and prognostications.
In this column, I'm starting a new mini-series on the future of FPGAs with analog as well as digital capabilities. Initially, we will initially cover FPGAs targeted specifically at power system control, but don't be surprised if you see other analog/digital hybrid FPGA devices discussed in future columns.
Today I will cover my discussions with Shyam Chandra, senior product marketing manager for mixed signal products at Lattice Semiconductor. Shyam is responsible for the platform and power Management devices. He has several years of experience in power supply control. He has even written a book on the topic, Power 2 You: A Guide to Power Supply Management and Control, which is available for free download in English, Chinese, and Japanese!
The growth in power supply complexity
Remember when power supply design just involved creating a 5V supply for your board? Granted, the amount of current was pretty large (a 24-pin bi-polar PAL could draw 200mA, so a handful of the devices could easily require several amps), but power typically wasn't an issue back in ye olden days. As Shyam explained, multiple supply designs began to show up with the migration to smaller CMOS processes and as the growing importance of lower power forced integrated circuits to run at reduced voltage levels.
Another trend -- the higher bandwidth input/outputs required to provide data to the new class of powerful compute engines (those for graphics, networking, and communications, for example) -- required these I/Os to run at reduced voltage levels, so signals could toggle fast enough to keep up with the data rates required to feed the beast.
Shyam also explained that, once multiple power rails began showing up, another issue surfaced: power rail bring-up. Not only did you need to control the ramp rate for each supply, but you also needed to control the sequence of bring-up, so that the I/O voltages and core voltages were in sync. An incorrect sequence would cause large current spikes that could initiate system resets, damage devices, instigate voltage drops, and trigger a host of other, sometimes unpredictable issues.
Even with proper sequencing, a large FPGA might require multiple amps during turn-on but only 1A during normal operation. If you didn't understand and plan for this, the FPGA configuration could be unreliable, and this would be a very difficult problem to isolate.
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