In today's column, I'm continuing a mini-series on the future of FPGAs with both analog and digital capabilities. We are initially covering FPGA's targeted specifically at power system control, but don't be surprised if you see other analog/digital hybrid FPGAs discussed in future columns. Today I continue my discussions, started in my previous blog, with Shyam Chandra, senior product marketing manager for mixed signal products with Lattice Semiconductor.
Improving reliability and reducing cost while simplifying power subsystem design
Last week we covered many of the features that new power subsystems require due to dramatically increased complexity. These features include multiple supply rails, multiple rail bring-up or shut-down constraints, hot-swap capabilities, reset sequencing, management of current spikes during FPGA initialization, and a host of other issues that make power subsystem design a real challenge. Shyam explained how programmable power control devices help simplify the design of these complex systems by centralizing control and implementing the required features with programmable analog and digital logic blocks.
Some of today's most difficult design challenges are related to improving system reliability, but without increasing cost or complexity. (We designers don't want much, do we? And what we do want we usually don't wish to pay much for or to have it make our designs more difficult!) Programmable logic once again comes to the rescue. By integrating more timing, sequencing, and monitoring capabilities, designers have the ability to implement reliability-focused features like failure detection, fault logging, margining, and trimming.
Shyam gave an example of a possible reliability issue in a multi-rail power subsystem design. Power-up and power-down sequencing can create not only functional issues (for example, if the memory isn't fully powered-up prior to the start of the initialization sequence for the FPGA, then the FPGA can be initialized incorrectly) but reliability issues as well. If rails are not sequenced correctly during power-down, the charge on the bypass capacitors can leak through the IC and -- over time -- will burn up the protection diodes. This can lead to unpredictable behavior and eventual chip failure. Correct voltage rail sequencing will alleviate this problem.
Another important aspect of system reliability is related to system testing. In order to rigorously identify out-of-spec components, it's becoming more common to perform multiple corner board testing. This involves the margining of supplies (raising or lowering a specific power rail by a few percent) to make sure that key components still operate correctly. For example, bringing the supply that feeds the 3.3V IO bank on an FPGA down by 5 percent while raising the 5V supply on the receiving MCU IOs by 5 percent might uncover either a DC issue (marginal logic low) or an AC issue (chips tend to speed up as the voltage goes up and slow down as the voltage goes down, thereby leading to delay or setup/hold timing violations at the outside range of the voltage specification).
Programmable power control devices can implement special margin functions to be used during system test that greatly simplify multiple corner testing. Additionally, the test routine can be programmed into the controller during system testing so that it need not be included in the shipped system, to reduce system cost.
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