Over the last few months I have been talking to experts in programmable logic about several key topics that have shaped, and will continue to shape, the industry. In this column, I will summarize what we have heard and chart some directions for future interviews.
This column is also an opportunity for you to add comments and questions on the topics you would like me to explore in future blogs. Let me know what and/or who you would like to hear from next.
As you may recall, several key topics popped up in my earlier discussions, and it's perhaps easiest to summarize some of these key topics in the form of a short "highlights reel." This will refresh our memories and provide some background for thinking about what topics we should ponder and who we should talk to next.
Steve Trimberger, Xilinx:
The increase in size of the FPGA lookup table (LUT) from four, to five, to now six inputs has facilitated optimization of the FPGA routing and logic mix. Larger logic blocks means that more routing can stay local (many times within the logic block itself). This improves silicon efficiency, reduces power dissipation, and improves performance -- all good things! Expect the trend to larger programmable blocks to continue.
Speculation: The current architecture using LUTs in general may finally run out of gas, causing a new architecture to emerge with a larger "grain" and easier expansion to heterogeneous implementations.
Navanee Sundaramoorthy, Xilinx:
The transition to MCU-oriented control in FPGA applications, coupled with the development of automatic algorithm partitioning, will simplify the high-level design of control-based algorithms. Control algorithms will eventually be defined at a high level, and the design software will be able to select the right target for the algorithm based on the required "control loop time."
Speculation: Even the MCU manufacturers will climb onto the programmable logic bandwagon. We will see many "hybrid" devices that combine one or more MCU blocks with multiple programmable fabric blocks. Development software will automatically partition functions into the appropriate blocks based on the desired performance and power consumption, coupled with resource availability.
Arif Rahman, Altera:
The development of special low-power operating modes to keep the growth in operating power in check will be required to enable continued growth in FPGA logic capacity. Without advanced functions similar to those in typical MCUs (sleep, stop, halt, etc.), FPGAs just can't scale fast enough to keep up with customer demand.
Speculation: The power controls offered with FPGA fabric will evolve to allow easier partitioning of low-power logic into special blocks with features like "sleep," whereby the logic is "turned off" until required, saving significant amounts of operating power. More than just "gating the clock," these modes will also result in dramatic reductions in static power consumption.
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