In this blog, I'm finishing a mini-series on the future of FPGAs and the IP cores that are critical component in making FPGA designs efficient.
In my previous column, I covered the challenges that face FPGA manufacturers as they develop and deploy IP cores to their customers. This was based on my discussions with Tim Vanevenhoven, director of marketing of IP design methodology at Xilinx. Now, I will move on to post some of my own thoughts on what the future challenges might be...
OK, my IP easily drops into my design, so am I done now?
As discussed in my last blog, Tim explained that the development of robust IP cores held out the promise of increased productivity to designers. Recent and dramatic improvements in FPGA design software tools, like those included in the Xilinx Vivado Design Suite, address some of the key barriers that were keeping IP cores from delivering on the design efficiency improvements designers were expecting (and in many cases paying for). For example, difficulties integrating IP, problems managing the collections of IP used by design tools, and issues with regard to interconnecting IP blocks needed to be addressed in order to remove the barriers to easily including IP cores in real-world designs.
With the recent advances having been made, everything should now work smoothly. The designer can just drop in a few IP blocks, easily connect them up, and hand off the finished design to the system architect... right? Well, these improvements have helped with the FPGA design part of the development, but there are still several tasks to do to get a complete design.
Verification and test
For the purposes of these discussions we are ignoring the process of adding "custom" logic to the design -- instead, we are focusing on the use of IP cores. In a future post I will discuss the advances we will need to design custom logic much more efficiently too, so look for that topic in a few weeks.
Keeping this in mind, once our design is finished, we still need to verify the design and test the design. Hopefully, the individual IP core blocks all work correctly, but making sure the design we have created by hooking a bunch of IP blocks together actually works as planned can be very difficult. In fact, the new ease with which we created our design has now pushed the majority of the development effort into verification and test! What logic do I need to add to send data into my design and check the results are as expected? How to I create enough test cases to make sure my design works in a wide range of situations? If my design is processing video or audio or data communications packets, this can be a daunting task.
Clearly, we need something to help us manage the large verification and test effort we will now face. This seems like another possibility for new IP developments! How about IP blocks that help us develop the necessary verification and test "platforms" our newly complex designs will require? In fact, there are some IP blocks like this -- pattern generators, results checkers, bus functional models, etc. -- that can be used, but in many cases these blocks don't have standard interfaces, have different latencies, and require "tweaking" to get them working together. Does any of this sound familiar?
Creating a robust set of easily generated and connected verification and test IP would seem to be the next area for significant improvement from FPGA manufacturers. In order to complement "one-click designing" using design IP blocks, we will need to have something like "one-click verification" to keep us productive. Does anyone out there know about something like this that is available today?
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