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Warren Miller

A Chess-Playing FPGA: The Evaluation Function, Part 2

Warren Miller
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Ruud Martin
Ruud Martin
2/6/2013 4:12:29 AM
User Rank
Beginner
Chess and FPGA
Warren,

This is my first post on this forum, but certainly not my last. I am slowly but steadily working and developing the same idea, on a Spartan 6 device. Still dreaming about a matrix of 100 XILINX FPGA (Xc3s4000), to support this idea, but this would probably pose a too big challenge for me. Maybe Xilinx has something lying around ;)

However, developing this in one big FPGA for a start is feasible. I will share my ideas on this forum as they progress, and will be following with great interest your steps in this matter.

For sure i am convinced this will work. Let set a limit tot end of this year to accomplish this task.. Evaluating 1 chess position per clk would be great, and thus achieving 100.000.000 nodes per second would be better. Remember that chess programs are doing at max 10.000.000 nodes per second on a multi core X86...

As you can see if you check on me and my company Phoenix Chess Systems building chess computer systems is no problem, using FPGA however is the next hurdle...

All the best,
Ruud

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shakeeb
shakeeb
2/3/2013 1:07:39 PM
User Rank
Beginner
Re: Linking to real-world use-cases
The concept of matching programing with the real world is really impressive.

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Max Maxfield
Max Maxfield
1/31/2013 12:04:34 PM
User Rank
Blogger
Linking to real-world use-cases
Hi Warren -- very interesting. I especially like things like when you say:

"...we could just 'pin' the value to the maximum permitted value (if we took our opponents king) or the minimum permitted value if they took our king. This saturating approach to the accumulation of piece value isn't unusual, since many functions want to avoid the 'overflow' of the accumulator and must 'pin' the values at the maximum and minimum of the range."

 

I love it when you tie what you are thinking about to real-world uses, such as saturating (or limiting) signals to some min-max values.

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