I have made sufficient progress in my chess-playing FPGA project that I'm going to start alternating back and forth between my "Chess-Playing FPGA" and "The Future of FPGA" posts, so in today's column we return to FPGA futures.
In this blog, I'm starting a mini-series on the development of Serializer/Deserializer (SerDes or SERDES) functions embedded in FPGAs. I discussed some of the background on SerDes technology in FPGAs with Mike Peng Li, Altera Fellow, and Salman Jiva, senior marketing manager for high-end products at Altera. Both Mike and Salman have many years of technical and marketing experience with SerDes technology as it applies to FPGAs. We started out talking about the key issues faced by FPGA suppliers over the last five years with respect to SerDes. (If you are new to SerDes technology, a good resource to use to review the basics is a DesignCon 2004 paper from Dave Lewis titled "SerDes Architectures and Applications.")
A short history of SerDes in FPGAs
SerDes functions have been available in FPGAs for several years. The growth in functionality of the SerDes is fairly well represented in the block diagram of the Altera high-speed serial transceivers used in the 40nm Stratix-IV FPGAs as illustrated below (click here to see a larger, more detailed version of this image):
In the early days, the embedded FPGA SerDes function (the hard coded portion not implemented in FPGA's programmable fabric) was just the Physical Media Attachment (PMA) portion of the overall subsystem; this is shown on the left-hand side of the diagram above. The designer needed to create (or use a supplied soft macro IP block) the Physical Coding Sublayer (PCS), which is shown in the middle of the above diagram. Also, examples of the PIPE or PCIe interface to the designer's logic are shown on the right-hand side of the diagram. Over time -- and as serial communications standards became more stable -- these digital elements of the design were converted to hard implementations, thereby saving a significant amount of the FPGA's programmable fabric, reducing power consumption and improving performance.
The PMA section includes a programmable equalization section. This acts as a high-pass filter to the data signal as it enters the receiver and rebuilds the signal so it can be interpreted correctly by the Clock Data Recovery (CDR) unit. The CDR circuit is used to extract a clock from the serial input, so that the data can be captured with the correct timing characteristics. The bit deserializer takes the correctly extracted serial data stream and creates a parallel data word for use in the PCS section. Converting to a parallel data word at this stage makes it easier to meet the aggressive timing requirements of high-speed communications standards.
The PCS section includes digital functionality to comply with a number of key protocols used in backplane, chip-to-chip, and chip-to-module applications. Examples of PCS functions are the 8b/10b encoder/decoder, phase-compensation FIFO buffers, word aligner, and rate matcher to deliver protocol compliance within the transceiver block. State machines can be included to support specific protocols like PCIe, GbE, and XAUI.
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