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Warren Miller

A Chess-Playing FPGA: Linking the Move Generator & Evaluation Functions

Warren Miller
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rfindley
rfindley
3/6/2013 2:51:21 PM
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Catching up...
@Warren,

I've been lagging behind in my APP reading, but wanted to mention that I'm looking forward to seeing more of this unfold -- especially as you get closer to doing some HDL coding!

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Max Maxfield
Max Maxfield
2/27/2013 12:10:14 PM
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Re: Caption should be 'Register' not 'Resister'
There you go -- it's been fixed

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Max Maxfield
Max Maxfield
2/27/2013 12:08:03 PM
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Re: Caption should be 'Register' not 'Resister'
Eeek, why didn't you tell me -- I will fix this immediately!!!

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Warren Miller
Warren Miller
2/15/2013 6:54:02 PM
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Caption should be 'Register' not 'Resister'
In case you were confused!

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More Blogs from Warren Miller
When traversing serial links with optics or backplanes, high-speed signals are degraded by impairments in the link, such as insertion loss, reflections, crosstalk, and optical dispersion.
Warren has finally started to write some HDL code to implement his chess-playing FPGA, but he's not a professional coder, so he needs our help and advice.
What might we see in new Ultra Low Density (ULD) CPLD families three-to-five years down the road? Are there new technologies or programmable structures that will find their way into ULD devices?
Following our evaluations, the resources required by a chess-playing FPGA implementation would seem reasonable, even for a small or midsized device.
A number of challenges are faced by the users and manufacturers of ultra-low-density devices (ULDs).
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