In this blog, I'm continuing a mini-series on the development of Serializer Deserializer (SerDes or SERDES) functions embedded into FPGAs.
In my previous post
on this topic, I discussed some of the background on SerDes technology in FPGAs with Mike Peng Li, Altera Fellow, and Salman Jiva, senior marketing manager, high-end products, from Altera. Today, we continue the discussion and review some of the key challenges facing SerDes technology in FPGAs. (If you are new to SerDes technology, a good resource to review the basics is a DesignCon 2004 paper from Dave Lewis, titled SerDes Architectures and Applications
In my previous post, we discussed how process node parity, market need for more flexible solutions, a compelling time to market imperative as standards were solidifying, and FPGA company involvement in determining and defining key elements of new high-speed serial interconnect standards created a perfect market window for FPGA companies. The result is that SerDes technology in FPGAs is now a key market driver. This doesn't mean that FPGA companies can rest on their laurels, however; more than ever, they must push forward with new features and capabilities to stay ahead of alternative implementation choices. Perhaps the best way to identify some of today's challenges is to review some key features that have been recently added to FPGA SerDes functions. This may also give us a good idea as to where this capability will be going in the future.
One of the most obvious challenges is the increasing number of serial communications standrads that an FPGA must be able to address -- legacy, established, and emerging. For example, at the 8Gb/s rate we see a range of established and legacy stadards for: PCIe 3.0, PCIe 2.0, Interlaken, Serial RapidIO, CPRI+, OBSAI 4.0+, STAT 3.0, SATA 2.0, SPAUI, DDR-XAUI, QPI, HyperTransport 3.0+, HighGig+, HighGig2+, OIF/CEI 6G-SR, OIF/CEI 6G-LR, and 4G FC (to name just a few).
Similarly, at 10Gbit/s we have legacy and established standards for: IEEE 802.3ba 40G/100G/10GBASE-R/10GBASE-KR, 10G PON/EPON, OIF SFI-S, OIF SFI-5.2 (40G), 10G Interlaken, SONET/SDH OC-192 (10G/40G), SFP+, XFP, OIF/CEI 11G-SR/LR, OTU2/3/4, 10G SDI, and 10G Infiniband.
And, as if all of this wasn't enough, at 28Gbit/s we see the following emerging standards: OIF/CE 28G-SR/VSR, IEEE 802.3ba 100G, 32G FibreChannel, and 25G Infiniband (so far).
Many of these standards have very specific requirements, so the SerDes designs used in FPGAs must be able to satisfy these requirements using a very flexible implementation, but without using too much power, increasing jitter, or increasing error rates. This presents a tough challenge, but one with which the FPGA manufacturers have some experience (and a few tricks up their sleeves) at overcoming.
Building a solid base
Perhaps one of the things the FPGA folks have created as a key core competency over the years is the ability to create some solid "foundation" capabilities that make it easy to then layer on top the more specific features required by specific SerDes requirements. As examples, very low jitter clocking and low power output drivers were used by Altera in the Stratix V SerDes designs. Low clock jitter will help improve all the other clock-related functions (and there are many) in SerDes designs. Low power drives will improve power efficiency of the typically power-hungry high-speed SerDes outputs on any standard interface implementation. Let's look at these two examples in more detail.
Control your jitter, Captain
A major component of jitter in a transceiver typically comes from the oscillator located within the PLL (phase-locked loop) circuit. Two of the most widely-used oscillator circuits are the Voltage Controlled Ring Oscillator (VCRO) and LC tanks (LCs). VCROs have a wide frequency tuning range, from 1 to100MHz to 1 to 10GHz. This covers a trmendously wide data rate, but the VCRO is sensitive to front-end noise spurs, power supply noise, and substrate noise. An LC offers superior phase-noise performance due to its highly selective and high-Q LC tank. With finer process geometries, it is now possible to integrate inductors on chip that occupy only a small amount of die real estate. Stratix V offers a ring oscillator and an LC oscillator as clock sources for the transmit (TX) clock. This allows the application to optimize for both the required frequency range and a small jitter budget.
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