I suggest a slight modification to your excellent waveform diagram. The "NEW" label should be moved rightward to the light blue section of the waveforms. This reflects the normal application of a transparent latch, while demonstrating all the points you make in your blog posting.
The latch normally opens before 'valid data' arrives at the input.
Valid input normally flows through the latch while latch is open
The latch normally closes while input data is still 'valid', extending the 'valid' time of the latch output.
Here is your diagram, with minor changes applied:
I like your colour coding -- it's a nice touch that definitely improves readability.
Max Maxfield 7/9/2012 9:43:34 AM User Rank Blogger
Re: Great explanation
@Celine: Make sure you check out Adam's 2-part article on Metastability in registers and latches http://bit.ly/NiNTUZ and http://bit.ly/MdlQXF (also note that the second part has two pages so you have to click the "more" link)
Thank you for this synthesis, I finally can get together the little pieces of knowledge that I had about the subject in a whole that makes sense. And I now really understand why I always avoided latches in my designs.
I forward the link for my fellow coworkers that intend to begin with FPGA !
I would imagine that most FPGA's consist of stages like this, i.e. enabled registers as you say a similar name would be enabled register as opposed to synchronous latch.
Every FPGA engineer should avoid latches I would hope, although I am sure our newer FPGA designers will inadvertantly create a few hence the blog attempting to explain what causes them and why they are not recommmended.
its probably unintentional, but the synchronous process figure description indicates it is a 'synchronous latch', but IMO, a less confusing description would be a register that only updates when enabled.
I personaly use stages like this whenever I am pipelining data with a valid strobe. I also use a variation of these regularly in single process FSMs (i.e., no default or else conditional).
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