In my previous blogs on the topic of driving a VGA (video graphics array) display, we first learned how to use an FPGA to generate the timing signals required to drive the display, and then we discussed the creation of an algorithmic test pattern generator. (See: Using an FPGA to Drive a VGA Display and Using an FPGA to Drive a VGA Test Pattern.)
As an aside, my co-bloggers here in All Programmable Planet have posted some associated columns, including Paul Clark, who is using multiple 8-bit PicoBlaze soft cores as part of his "Game of Life" implementation that will present its results on a VGA display. (See: Why PicoBlaze? FPGA-Based Game of Life.) Also, Max Maxfield posted a blog on using FPGAs to generate 24-bit color images, followed by a blog on using FPGAs to generate different color depths. (See: Ask Max: Using FPGAs to Generate 24-Bit Color Images and Ask Max: Using FPGAs to Generate Different Color Depths.)
Returning to my test pattern generator... the next step is to create a more sophisticated implementation that uses external Double Data Rate 2 (DDR2) DRAM to store a downloaded image and then display it using the VGA. This is an adaption of how many imaging systems work, in that they will buffer up a complete image to be output while processing the next image in a series -- often using banks of Double Data Rate (DDR) or Quad Data Rate (QDR) memory to achieve this. This ability to store the image will hopefully be of use in Max and Duane’s robot avatar project, as it will allow the storing of an overlay that can be projected on top of a live image. (See: Creating an FPGA-Based Robot Avatar.)
The last time I discussed this, I included a simple architecture diagram showing my first thoughts as to how we could implement this system. However, as with all initial architectural concepts, when it came time to actually generate an architecture, I ended up revising my ideas and -- hopefully -- simplifying things a little.
The block diagram shown below reflects the main functional blocks (click here
to see a larger, more detailed version of this image):
As we see, the current version of the design consists of the following units:
- RS232 Interface: Receives the image at 115,200 bits per second (Bp/s) from a PC. (One possible improvement for the future would be the use of Ethernet communications.)
- VGA Timing Generator: Generates the VGA timing waveforms we have discussed in my previous blogs.
- Memory Interface: When configured for storing an image, this module connects to the RS232 interface and stores the image in the DDR2 DRAM. When configured to display an image, this module reads out the image line-by-line from the DDR2 DRAM as required to by the VGA protocol.
- Line Store: A FIFO (First-In First-Out) memory that stores the line to be output (as one line is being read out another is being stored).
Over the coming weeks, we will be looking at the development of each block in detail. Meanwhile, in the remainder of this blog, I will be explaining a little more about the overall architectural design of the FPGA.
Next page >