In my previous blogs on the topic of driving a VGA (video graphics array) display, we first learned how to use an FPGA to generate the timing signals required to drive the display, and then we discussed the creation of an algorithmic test pattern generator. (See: Using an FPGA to Drive a VGA Display and Using an FPGA to Drive a VGA Test Pattern.)
Returning to my test pattern generator... the next step is to create a more sophisticated implementation that uses external Double Data Rate 2 (DDR2) DRAM to store a downloaded image and then display it using the VGA. This is an adaption of how many imaging systems work, in that they will buffer up a complete image to be output while processing the next image in a series -- often using banks of Double Data Rate (DDR) or Quad Data Rate (QDR) memory to achieve this. This ability to store the image will hopefully be of use in Max and Duane’s robot avatar project, as it will allow the storing of an overlay that can be projected on top of a live image. (See: Creating an FPGA-Based Robot Avatar.)
The last time I discussed this, I included a simple architecture diagram showing my first thoughts as to how we could implement this system. However, as with all initial architectural concepts, when it came time to actually generate an architecture, I ended up revising my ideas and -- hopefully -- simplifying things a little.
The block diagram shown below reflects the main functional blocks (click here to see a larger, more detailed version of this image):
As we see, the current version of the design consists of the following units:
RS232 Interface: Receives the image at 115,200 bits per second (Bp/s) from a PC. (One possible improvement for the future would be the use of Ethernet communications.)
VGA Timing Generator: Generates the VGA timing waveforms we have discussed in my previous blogs.
Memory Interface: When configured for storing an image, this module connects to the RS232 interface and stores the image in the DDR2 DRAM. When configured to display an image, this module reads out the image line-by-line from the DDR2 DRAM as required to by the VGA protocol.
Line Store: A FIFO (First-In First-Out) memory that stores the line to be output (as one line is being read out another is being stored).
Over the coming weeks, we will be looking at the development of each block in detail. Meanwhile, in the remainder of this blog, I will be explaining a little more about the overall architectural design of the FPGA.
Sounds AWSOME Max but I too did try something similar but it became a bit boring since it took off my time in developing somthing cool than writing it.
Adam, am totally agree with you. But it seems that most of the engineers are not showing enough interest to diversify their skills to allied or associated areas. Instead of being as an all rounder they used to prefer as an expert in their area of work. One main reason is lack of time and second could be lack of interest. But I personally prefer to be an all rounder, it will help them in managerial level to handle issues in much better way.
Adam Taylor 8/14/2012 1:43:25 PM User Rank Blogger
Re: Why DDR RAM?
@Myplanet sorry it just all came out as I was writing my reply to Paul ;)
FPGA engineers should not see themselves as just programmers I am a stong believer that to be a good FPGA engineer you must also be a Hardware / Systems engineer who is capable of working on board level or system level solutions. Therefore helping to define the system soultion the coding is often the easy bit the definition of the system, algorithm, hardware, interfaces etc is what takes time.
Even on slow 8 bits I have come up against speed problems especially with serial EEPROM'S needing wait states to be inserted between writes.
As you make the point, this is where the balance between speed and cost comes in. For a particular job I discounted cost and used a serial F-RAM which provided much greater write speeds.
Adam, from VGA display topic you had moved to memory. Ofcource memory is a major part in hardware side and I think we have to cover some topics about both volatile and static memory, through some additional blogs. In most of the cases, programmers have no role in selecting the memory type because such things are taken care by the design engineers.
Adam Taylor 8/13/2012 1:10:52 PM User Rank Blogger
Re: Why DDR RAM?
Paul,
This would make a good topic for a blog on its own, why use one technology of memory as opposed to another for storage.
Typically the first choice a system designer will take is do i need non volatile or volatile storage. If you need to rememeber data between power cycles then you need non volatile.
This then becomes a subject of can I run the programme from the non volatile memory or do I need to cross load this into a faster volatile memory (i.e. boot loader on many software applications which stores data in non volatile memory but cross loads the memory to RAM at start up and runs from there).
The main reason I went with using DDR is it is what I had available and I thought I would it would be of use as controlling a DDR ram is interesting.
Typically when selecting a memory technology your system requirements will drive you're selection the main drivers are
Bandwidth and Speed
Latency
Cost (often overlooked)
Storage Capacity
Power Consumption
For volatile memory this comes down to choice between Dynamic RAM technologies (SDRAM, DDR) and Static RAM technologies (SRAM, QDR etc). DRAMS are typically lower cost, higher latency, higher storage capacity and higer power dissipation. Along with higher complexity of controlling the refresh, read and write cycles as well.
The end application will also come into play QDR are particularly suited when you are doing 50:50 read and writes. DRAMS are better for busrts of accesses.
Of course if you can fit the storage within the FPGA then you would be in most cases best of doing that. In this case I could not store the image internally in the FPGA.
As engineers designing the system it is our job to implement elegant and cost effective solutions (while we enjoy engineering nice solutions the end goal is to make a product that makes our employers a profit) So a trade off of technology types might be in order for more complex systems.
Max Maxfield 8/13/2012 12:30:18 PM User Rank Blogger
Re: Why DDR RAM?
@Paul: I think it was a limitation with the amount of BRAM (block RAM) in Adam's FPGA and the fact that he had DRAM on his dev board ... but I'll let him answer for sure...
In which we discover how to create a custom peripheral in the Zynq's programmable fabric in such a way that it can be controlled by the Zynq's processing system.
Here we discover how to use the XADC (Xilinx Analog-to-Digital Convertor) in the Zynq All Programmable SoC to read the chip's internal temperature and voltage parameters and output them over an RS-232 link.
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