As I touched upon in my earlier column on metastability, a VHDL signal that uses the "std_logic_1164 package" can undertake one of nine different values. (See: Ask Adam VHDL: Metastability, Part 2.)
This may come as a shock to newer FPGA designers, who might wonder why a signal that spends the majority of its time as a 0 or 1 needs seven other values to accurately represent its behavior. As with a lot of these things, there is an interesting history as to why we ended up with this nine-value system.
These nine values are defined by the IEEE standard 1164, which was introduced in 1993. This replaced the earlier IEEE 1076-1987 standard, whose logical type -- the "bit" -- could assume one of only two values: 0 or 1. Sadly the "bit" type's limited value system caused issues with models of buses, in which multiple tri-state drive gates may be connected to the same signal.
In order to address this problem, the multi-valued logic system defined by the IEEE 1164 standard not only introduced a set of new values, but it also defined an order of precedence. This order of precedence is very important to ensure that the simulator can correctly resolve the value on a signal.
Another way of visualizing this graphically is illustrated below. What this image tells us is that a conflict between a signal carrying a "U" (Uninitialized) value -- for example, a register that has not been loaded with a 0 or 1 -- and any other value will result in a "U." A conflict between a "-" (Don't Care) value and any other value (apart from a "U") will result in an "X." A conflict between a "0" and a "1" will result in an "X." A conflict between a "0" and an "L," "W,", or "H" will result in a "0." And so on and so forth...
It's important to note that not all of these values can be assigned in synthesizable code, but they may be used in modeling and -- in the case of the "U" (Uninitialized") value, for example -- they may be seen as the initial values on signals and registers during simulation.
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