Adam Powers Up His Zynq ZedBoard, Part 2

As you may recall, when we last parted company at the end of Part 1 in this mini-series, we were just about to create the processing system.

Having clicked on the "Add or Create Embedded Sources" option, you will be presented with the ability to select a name for the processing system you will be creating, Being original as always, I chose to name mine "processor_subsystem," as illustrated below:

Following this, you will be taken through a number of stages to create a Base System using what is called the "BSB wizard," as illustrated below:

Next, you will be pseudo-prompted to select the bus structure you wish to use -- AXI or PLB. The reason I say "pseudo-prompted" is that you really don't have a choice here because the PLB option will be greyed out allowing only the selection of the AXI bus, as illustrated below. (Click here to see a larger, more detailed version of this image):

The next screen will ask you to confirm the version of the development board we are targeting. As I mentioned in my previous column, for some reason or other there is no ZedBoard option at this time, so we shall instead target the Zynq ZC702 Evaluation Platform, as illustrated below. (Click here to see a larger, more detailed version of this image):

This will result in the opening of Xilinx Platform Studio, at which time you will be presented with a graphical representation of the processing system within the devices. If, like me, you encounter any licensing issues, then please follow the steps outlined here.

At this stage, we have almost completed the implementation of the processing system. However, as I mentioned earlier, we are currently targeting the Zynq ZC702 Development Board and not the ZedBoard we are actually using. In order to correct this we first need to download the appropriate board definition file by clicking here.

Board definition files define how the Zynq's processing system interfaces to the external world and includes things like DDR memory timing. If you were developing your own design with the Zynq on a custom PCB, this stage could be quite time consuming. Fortunately, the creators of the ZedBoard have already done this for us -- thanks to the board definition file we can easily reconfigure the design for the ZedBoard environment. Having imported this file, you should see some obvious changes -- particularly in the I/O peripheral column -- as illustrated below. (Click here to see a larger, more detailed version of this image):

While in the "System Assembly View" window, select the "Bus Interfaces" tab and check that the "LEDs_8Bits" show they are connected to the "axi4lite" bus -- that is, they do not show "not connected" -- as illustrated below. (Click here to see a larger, more detailed version of this image):

Next, click on the "Ports" tab and check that the LED outputs are declared as external ports and are connected to the external pins, as illustrated below. (Click here to see a larger, more detailed version of this image):

The final step within XPS is to run a design rule check to ensure we have created a system which complies with the design rules. We do this by clicking the "Project" menu and selecting the "Design Rule Check" item from the resulting options, as illustrated below. (Click here to see a larger, more detailed version of this image):

Once everything has checked out, you can close XPS and return to PlanAhead, which we are going to use to generate the RTL netlist, pin constraints, and a configuration bitfile. At this point, we have defined what the processing system will contain:

1. The processing system (PS) section with DDR, UART, Ethernet, USB,SD, GPIO, and Flash memory support.
2. The programmable logic (PL) section containing one AXI slave connected to a GPIO module interfacing to the LEDs.

The final remaining steps before a configuration bitfile can be generated are to generate an HDL netlist and create a constraints file containing pin-out information for the PL side of the Zynq. This can be generated in either VHDL or Verilog as defined via the project settings. Generating this HDL file is as simple as right-clicking on your processing system name and selecting the "Create Top HDL" option, as illustrated below. (Click here to see a larger, more detailed version of this image):

The constraints file can be created within PlanAhead by right-clicking on the "Constraints" option in the source window and selecting the "Add Sources" item. This will allow you to create the file. Within this file you will need to type the following to connect the GPIO slaves in the programmable logic section to the correct IO.

Note that you can obtain the schematics for the ZedBoard, along with a wealth of other information from the "Documentation" area on the ZedBoard.org website.

You can now use PlanAhead to generate the configuration bitstream. In order to do anything useful, however, we will first need to write some software -- I will cover this topic in my next column.

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• Using an FPGA to Drive a VGA Display
• Using an FPGA to Drive a VGA Test Pattern
• ChipScope In-Chip FPGA Virtual Logic Analyzer
• A More Sophisticated FPGA-Based VGA Display
• Are Your FPGA Designs Secure?
• MTBF & FPGA-Based System-Level Reliability
• FPGA-Based System Reliability: Tips & Tricks
• UKube: Xilinx SRAM-Based FPGAs Are Spacebound
• Space FPGA User Workshop Day 1: European FPGAs
• Space FPGA User Workshop Day 2: Non-European FPGAs
• Adam Powers Up His Zynq ZedBoard, Part 1

"Ask Adam" posts:

• Ask Adam VHDL: Sensitivity Lists & Simulation
• Ask Adam VHDL: Coding Styles
• Ask Adam VHDL: Registers & Latches
• Ask Adam VHDL: Metastability, Part 1
• Ask Adam VHDL: Metastability, Part 2
• Ask Adam: UART, SPI, I2C & More
• Ask Adam VHDL: Logic Values
• Ask Adam VHDL: Handling the Don't Care Value
• Ask Adam: FPGAs & RS-232
• Ask Adam VHDL: Edge Detection on Signals