A small, French startup -- Flexras -- made a few waves at the 2012 Design Automation Conference (DAC) with an FPGA prototype partitioning tool called Wasga Compiler. In their press release, the folks from Flexras described this tool as being "Unique and the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping."
Now, when I read absolutist hyperbole like this, my teeth begin to itch, so I thought I'd make a meeting request and check out these claims. Below you can see my video interview. After you watch it, I have a few questions:
After the interview, I hightailed it over to the Xilinx stand and asked if this tool actually worked as advertised. The folks at Xilinx confirmed that Wasga did, in fact, "show great promise" in initial trials. This is actually high praise from a company that needs to maintain neutrality. The truth is that the Wasga Compiler may not be the "first" timing-driven tool for this application, but it is based on a unique algorithm and approach to timing that delivers both speed over manual partitioning and superior performance over competing tools.
So, here are my questions for you:
Which is the biggest problem for you in partitioning -- performance or the time it takes to do it?
Are the free tools good enough combined with manual partitioning?
Do you actually prefer manual partitioning, but use commercial tools -- even though they don't deliver great results -- to get you far enough to do your manual work?
Would you take a flier at the Flexras tool in the hope that you'd actually get your work done completely?
And one last question: Does press release hyperbole make your teeth itch, too, and how do you respond to it?
Even 1900, it grows slower then the logic capacity ( 2 Million Lut for the V7). It does not follow the moore law, neither the Rent's rule.
The number of pins in FPGA fits quietly the requirement of an application or an IP that needs one FPGA. Enough pins for the limited number of IO in the top of a design to connect to interfaces.
However, in the rapid prototyping of large SoC/ASIC( tens or hundreds of million ASIC gates), the design will be splitted onto multiple FPGA, complex IPs and modules will be partitioned: millions of ASIC gates equivalent per device, and the cut between them can be of thousands of signals.
Note: do not count the clock IOs, and if we need robustness ( for designs that will run for hours with high temperature), we use LVDS and we divide the number of IO per more than 2
I think if you are looking for the sheer number of pins on an FPGA, Brian, you are right, but Hader is making the point that the number of LUTs per pin gets progressively lower the larger the FPGA, which is were the partitioning gets a little dicey.
Indeed, FPGA LUTs follows moore's law ... but pins don't. The number of pins per K LUTs for "Virtex2", "Virtex4", "Virtex5", "Virtex6", "Virtex7" is "11.9", "5.4", "2.9", "1.3", "0.5" respectively.
FPGA is starved for pins and it's getting a big challenge for the prototyping.
The pin-muliplexing ratio depends also on the design congestion (including modules and signals for debug). With Flexras partitioning most critical paths are not multiplexed, and less critical paths are routed through the multiplexed IO. Typically the pin-multiplexing ratio (or size) varies from 1 to some tens.
Brian Bailey 6/11/2012 1:06:59 PM User Rank Blogger
Tradeoffs
I also interviewed Flexras at DAC and will be posting that in the future, but I did not perform a technical interview and I will have to follow up with these guys to get more details. Most of the time, it is the pins of the FPGA that provide the biggest limit to multi-FPGA prototypes. To get around this, many prototyping solutions actually multiplex the pins so they can have more virtual connections that physical. I have to wonder with Flexras what their typical utilization rates are.
Max Maxfield 6/8/2012 5:29:37 PM User Rank Blogger
Great Video!
Hi Lou -- thanks for this -- I really like the idea of these video interviews.
Not everyone can afford the time or money to attend things like DAC. We all see lots of press releases and suchlike, but it's great to see things like these video interviews where you get to ask the questions we would all like to ask.
I hope we can expect to see more of these in the future...
When industry giant Qualcomm and tiny startup Esencia were named "best of show" at ARM TechCon, Qualcomm didn't send anyone to collect their award at the keynote, but Esencia was there with bells on.
This is the challenge I place before you. Would it be possible to create an FPGA-based implementation of the Great Highland Bagpipes that has all the nuances of the real thing?
There are a number of reasons a system architect or design engineer might choose one FPGA vendor over another, but would there be some advantages to having a truly agnostic system foundation?
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