Recently -- for reasons we don’t need to go into here -- I tried to make my FPGA transmit AM (amplitude modulation) shortwave. It failed badly. It couldn't even manage to send an SOS message in Morse code across a large room. But just last night, I tried to transmit using FM (frequency modulation), and it worked like a charm!
This all came about a week or so ago while I was helping somebody to get the OSERDES2 drivers working on a Digilent Atlys Spartan-6 FPGA Development Board.
Actually, before we proceed further, perhaps I should take a step back and note that the term SerDes (Serializer/Deserializer) refers to a pair of functional blocks that are commonly used in high-speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. As you may know, Spartan-6 devices contain input SerDes (ISERDES) and output SerDes (OSERDES) blocks. These primitives simplify the design of serializing and deserializing circuits to facilitate higher operational speeds.
In fact, this was a more than worthwhile task, as in the process I learned quite a bit about how the clocking works within the I/O banks on the Spartan 6 (it's not quite as straightforward as it seems on the surface).
One of the good things about the SerDes cores on an FPGA is that they can generate high frequency signals. I started wondering if an OSERDES2 block could be hooked up somehow to generate precise high frequencies. Maybe by dropping a bit "here" or by stuffing in an extra bit "there."
I toyed with the idea in my head a little, and then I forgot about it and moved on to something else.
Sometime later, somebody else was chatting about an FPGA based front-of-house audio box he had created (8 channels in; 12 channels out; all digital switching implemented in an FPGA). He mentioned that he had also added a few sine wave generators -- I guess they're for use in setting up the mix. Apparently, these sine wave generators employ a "phase accumulator" to index a table of sine values, and the generated value is passed via the switching matrix (implemented in the FPGA) to the DACs (digital to analog converters) for conversion into audio outputs.
This is all pretty neat stuff. The use of phase accumulators allows the generation of very precise audio frequencies. It seems that this project was built out of reconditioned, professional-grade audio DAC/ADC boards the designer had reverse-engineered -- very much a labor of love.
Tonight, I finally decided to try to synthesize a broadcast-band FM signal. After consulting the Internet, I discovered that FM uses +/- 75kHz modulation (for example, 91.0 FM covers 90.925MHz to 91.075MHz). In order to transmit Morse code, all that is required is to switch the phase accumulator between generating each of these three frequencies.
Initially, I thought this level of precision was going to be hard to obtain. In practice, however, it's quite easy -- all you need is a phase accumulator with a one-bit output (since I don't have a high speed DAC, no sine wave lookup table is required).
Running a few numbers, I decided that a 32-bit accumulator looked about right. This is large enough to obtain good frequency accuracy (approximately 12 bits of resolution), but not so large that that the size of the adders limits clock speeds.
An hour later I had a working FM transmitter. What surprised me was the reception range. My home is located on a half-acre lot, and with just a random piece of wire as the transmitter's antenna, I can go all the way to the back fence and still get a good signal. The video below shows a demonstration of the range of my simple FM transmitter implemented in a Papilio Plus FPGA development board.
Should you wish to take a more in-depth look at this project, you will find it at my HamsterWorks Wiki. As you will see, this requires a surprisingly small 60 lines of VHDL.
This turned out to be a quick, simple project -- a pleasant surprise when working with FPGAs! But now I'm left wondering -- in which project am I going to employ an FPGA-based FM transmitter?
AXI is actually surprisingly easy to implement, with the help of EDK the one thing which catches people out is the fact that the only memory controller which you can use of the zedboard is the one in the Cortex hardcore, using any softcore memory controller isnt going to work because there is nowhere for the pins to connect to.
EDK is easy to use as long as you dont break it as I managed to do today.
I went ahead and wrote up about 600 words on STA, PVT, and how commercial shops often get by with less costly FPGA's if they do not use the full temperature range of the parts or are doing low quantities or similar. The Blog will apear Jan 17th.
You just might be able to get away with it -- that 464MHZ is at the min for V core, with the slowest -1 part in that speed bin, and +70 or +85 deg C. The average part in the bin at 25 deg C is likely faster even at close to min for V core. (PVT)
On a most probably related issue, I had just a twinge of disappointed when I realised my project had defaulted to speed grade '-3', and the board has a '-1'.
I'm just about to embark on reading documentation on how to implement a AXI bus master (or something like that) so I too can put my frame buffer into SDRAM.
If I were an evil genius working on a plan for world domination (with regard to enterprise-level data storage solutions) I would be seriously considering building my design around a Zynq All Programmable SoC.
I would like to present to fellow readers of All Programmable Planet a new technique that I have invented to serialize data within the FPGA's main fabric at 1.5Gb/s.
As with most things, my feeling is that there is no better way to understand high-speed serial links than to implement one from the ground up, so that is what I've set out to do.
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