One of the features that the Xilinx Spartan-6 series of FPGAs has over their older Spartan-3E cousins (ancestors?) is the ability to reprogram the DCM (digital clock manager) block's multiply and divide ratio "on the fly," thereby allowing you to dynamically change the clock signals being generated by the Digital Frequency Synthesizer.
Programming is achieved with a dedicated Serial Peripheral Interface (SPI) bus. (See also the Using the SPI Bus columns by my fellow All Programmable Planet blogger, Duane Benson.) First, two ten-bit words are written, with the initial 2-bit value indicating whether it is the multiply or divide register that is being updated, followed by the new 8-bit value for the register. The values used are the "terminal counts," which means they are one less than the actual multiply or divide values you require.
Once these two words have been sent, a single "0" bit is transferred to start the DCM's reconfiguration. There is a minimal gap requirement between these transactions of one or two cycles.
Coding this in a HDL (hardware description language) is pretty easy. Here's my design in VHDL (click here to see a larger, more detailed version of this image):
And here is how to add a DCM_CLKGEN component in your design and connect up the programming signals:
If you plan to switch modes often, then you should also monitor the "PROGDONE" line to check that programming completes correctly. Also, you can monitor the "LOCKED" signal to see when the DCM has correctly synchronized and is now generating the new frequency (this can take up to 5ms).
I've still got a few questions, such as what happens if the DCM's "RST" (reset) signal is asserted? Do the registers default back to their "generic" values? Maybe a few minutes at my test bench are required.
And there you have it -- how to switch clock frequencies on the fly! Now, the next question is: Can you think of anywhere you might want to use this technique?
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