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Mike Field

1080p DVI-D With a Spartan 6 LX FPGA? Yes!

Mike Field
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Brian Davis
Brian Davis
3/9/2013 9:53:40 PM
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Clever Clogs
high speed routing notes
Looks neat, is 3D HD video support next in line at the Hamsterworks ? :)

A few notes below:

 - Stupid Routing Tricks
 - Virtex-E DDR-in-fabric application note
 - Output Buffer supported bandwidth = 1050 Mbps

-Brian

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Stupid Routing Tricks

 Once the primitive location has been locked down in applications such as this, it is useful to force the router to use a specific routing resource. This can be accomplished either using MAXDELAY or DIrected Routing consTraints (DIRT)

 For MAXDELAY's, look at the delay on direct path you want to use in the FPGA editor, then double that time and place that MAXDELAY on the net as a starting point. IIRC, if you start too close to the shortest route delay, the tool sometimes just gives up on the net. Then look at the results, and tighten up the MAXDELAY as needed.

 DIRT's tell the tool **exactly** what routing resources to use, but they are harder to create from scratch; they can be exported from FPGA Editor given a routed net.
See:
http://www.xilinx.com/support/answers/35556.htm

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Virtex-E DDR-in-fabric application note

 The first Xilinx family supporting LVDS, the Virtex-E, lacked the DDR output flip-flops of the later families; a similar XOR technique, sourced from CLB FF's, was used to support the 622 Mbps LVDS outputs.

See:
http://www.xilinx.com/support/documentation/application_notes/xapp233.pdf

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Output Buffer supported bandwidth = 1050 Mbps

 Note, the following is intended as an observation, not a criticism.

 Although you have avoided the specific clock rate restrictions of the output flip-flops and OSERDES blocks, bear in mind that the differential output buffer itself has a finite bandwidth, which also limits the output performance of the part.

 The front page of the Spartan-6 datasheet lists a maximum data rate of 1050 Mbps, but I did not see any specific info in the AC specification section of the datasheet on the output buffer proper sans FF or OSERDES.

 Internally to the FPGA, the single ended logic nets also tend to have some rise/fall asymmetry, which will affect the XOR output pulse width in an application such as this.

 Although this might work well on a given board and part, and is certainly fine to try for a homebrew project, I expect you are running considerably beyond the rated buffer performance.

 Looking at the S6 IBIS model TMDS reference switching waveforms should give an indication of how far the buffers can swing @ 1500 Mbps.

 You do not need a full IBIS simulator to inspect the models, something like the free viewer mode of Edality's IBIS Develpment Studio will work:
http://www.sintecs.eu/content/ibis-development-studio



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Max Maxfield
Max Maxfield
3/5/2013 6:24:18 PM
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Re: You never fail...
@Hamster: The apple does not fall far from the tree :-)


LOL

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hamster
hamster
3/5/2013 6:22:09 PM
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Re: You never fail...
@Max, He loves his walks, but not as much as he loves his iPad. His first word was iPad.

He rolled out of the lounge and into the kitchen, found his communication placemats that we were teaching him to use at the table, sorted through them to he found the correct "play time" one, and then started repeatedly tapping the iPad picture...

The apple does not fall far from the tree :-)

 

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Max Maxfield
Max Maxfield
3/5/2013 5:38:17 PM
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Re: You never fail...
@Hamster: He has a rare/unique genetic condition...

I am so sorry about this -- I remember your mentioning it before -- but he's lucky to have such a wonderful dad -- I bet he loves taking walks with you.

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hamster
hamster
3/5/2013 5:24:25 PM
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Re: You never fail...
5+1/2, but is really only about 18 mths. He has a rare/unique genetic condition, undiagnosed as yet but looks to be a genetic mosaic condition. It has caused lots of neurological damage and physical issues...

 

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Max Maxfield
Max Maxfield
3/5/2013 4:59:03 PM
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You never fail...
Hamster -- you never fail to amaze me -- this is very, very clever.

How old is your son?

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