As you are no doubt aware, the Xilinx Zynq-7000 All Programmable SoC is much more than a 28nm FPGA with 85,000 7 Series programmable logic cells -- it also contains a dual ARM Cortex-A9 32-bit microcontroller as a hard core, which makes it a very powerful system suitable for all manner of high-speed embedded applications.
One of the first questions that arises when dealing with a highly complex device such as this is how do we get the programmable logic (PL) portion of the device to communicate with the processor system (PS) part of the chip? Also, how do we get our blocks of programmable logic -- our IP blocks -- to talk to each other in a consistent and scalable manner?
When dealing with smaller, less complex FPGAs, it used to be that designers were often content to implement ad hoc interfaces between various IP blocks. While feasible for small designs, this approach isn't very easy to maintain; any change in the requirements for a particular IP block often mean a change to its interface, which then requires time-consuming and costly rewrites of the code, retesting, and so on and so forth. This is clearly not an ideal scenario when it comes to a large design where there are many engineers working on different parts of the system.
One way to make this type of system design easier to maintain and modify and is to use the idea of a single type of interface bus, which provides a single interface protocol across all IP blocks. Of course, it is necessary for this bus to support differing requirements, because you might have some IP blocks that require only a very simple one-way transfer of a few signals, while others may demand the full duplex transfer of vast amounts of data at very high speed.
And so we come to the Advanced eXtensible Interface (AXI), which is the third generation of ARM's AMBA interface. Defined in the AMBA 3 specification, AXI is targeted at high-performance, high-clock-frequency system designs, and it includes features that make it very suitable for high speed sub-micrometer interconnect:
- Separate address/control and data phases
- Support for unaligned data transfers using byte strobes
- Burst-based transactions with only the start address issued
- Issuing of multiple outstanding addresses
- Easy addition of register stages to provide timing closure
Of course, there are all manner of interfaces that have been defined for connecting IP blocks in FPGA and ASIC designs, but an increasing number of IP vendors and device manufacturers are now supporting the AXI interface. The folks at Xilinx adopted the AXI protocol for IP cores beginning with their Spartan-6 and Virtex-6 devices. Now they are using AXI in the Zynq-7000 All Programmable SoC to allow the Cortex-A9 processor system to communicate with, and control, custom logic implemented in the programmable fabric.
You can discover a lot of useful information in the Xilinx AXI Reference Guide, but a brief summary is as follows. Basically, AXI operates in three different modes:
- AXI4-Lite for simple low throughput memory mapped interfaces
- AXI4 for high performance memory mapped interfaces
- AXI4-Stream for high speed streaming data
Both the AXI4 and AXI4-Lite protocols define five different channels:
- Read Address Channel
- Write Address Channel
- Read Data Channel
- Write Data Channel
- Write Response Channel
Data transfer sizes can vary, and data can move in both directions between the master and slave simultaneously. The limit in AXI4 is a burst transaction of up to 256 data transfers; AXI4-Lite allows only one data transfer per transaction.
Meanwhile, AXI4-Stream defines a single channel of streaming data. This is modeled after the AXI4 Write Data channel, but unlike the AXI4 and AXI4-Lite protocols, it is not limited in the size of data bursts that are allowed.
There are many ways in which these interfaces can provide high-performance data transfers, including burst read and write cycles, out-of-order transaction processing, and data upsizing and downsizing.
The upshot of all this is we now have one common interface among our IP blocks. This interface can handle the various types of extremely complex and unpredictable data transfers that can occur in modern embedded systems; however, we -- as the designers -- are required to learn only one protocol.
In my next blog on this subject, I want to talk in more detail about using the Xilinx EDK, SDK, ISE, and PlanAhead tools to design a system that uses the simplest AXI interface -- AXI4-Lite -- to allow the Cortex-A9 processor system to communicate with, and control, custom logic implemented in the programmable fabric.
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