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Bill Schweber

Ready for JESD204B? Maybe You Should Be

Bill Schweber
SA_Penguin
SA_Penguin
12/23/2012 6:46:39 AM
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Expert
JESD204 - and pin reduction
There's a problem with reducing the number of pins / tracks in use, by going to JESD204 or a variant. Sure, the number of tracks goes down ( http://www.edn.com/design/analog/4401737/Why-JESD204B-may-solve-a-lot-of-your-system-design-headaches ) but that's not the end of the story.

If you aren't using an Artix-7 XC7A20SL, or Zync XC7Z010, your minimum pin count is: 484 pins. On the Virtex-7 it's 1157 pins. If you ARE using one of these two, your minimum pin count is 236.

Much as I'd like to see a new Spartan-6 variant 144 pin QFP, supporting JSD204a or b, it's not going to happen. board space, circuit complexity, even development software need to be changed to match the new target FPGA's

 

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bicyclebill
bicyclebill
11/5/2012 8:58:52 AM
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Blogger
Re: Cannot Wait
Of course, it will be situation as usual, and no technical advance will go "unpunished. What will happen is that the physics folks at CERN and similar will likely take a serial JESD link, but then use bundles of them as a large parallel set of these serial links. So the number of interconnects will be back up to where it was--although, admittedly, with many, many more high-speed channels.

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Adam Taylor
Adam Taylor
11/5/2012 6:51:50 AM
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Blogger
Cannot Wait
A subject very close to my heart at the moment, the use of High Speed Serial Links in palce of parallel buses for high performance DAC's and ADC's will be a step in the right direction. We just need to get them space qualified also ;)

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