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Bill Schweber

FPGAs + ADCs = Good Enough?

Bill Schweber
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JezmoSSL
JezmoSSL
11/17/2012 3:06:10 PM
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Re: Swap it around
I am kind of busy saving the world, its o.k you can thank me later

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Adam Taylor
Adam Taylor
11/17/2012 12:21:55 PM
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Re: Swap it around
Lol I am happy to write it if you have no objections. 

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JezmoSSL
JezmoSSL
11/17/2012 11:58:15 AM
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Re: Swap it around
Yeah,I dont like the way he looks at me when he says 'One of us'

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Adam Taylor
Adam Taylor
11/17/2012 9:29:21 AM
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Re: Swap it around
I thought it might be ;) we do a lot of beam forming and phase is very importnant in that application also.

Good quality clocks are key and a good distribution network is very important might be worth one of us doing a blog about it. 

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JezmoSSL
JezmoSSL
11/17/2012 7:35:33 AM
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Re: Swap it around
Phase is very important, if you have a stereo signal and one channel is even slightly out of phase with the other then you get a very nasty comb filter effect.All the ADCs are synced by a master clock which is derived from the serial data link syncs symbols.

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Adam Taylor
Adam Taylor
11/17/2012 7:17:15 AM
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Re: Swap it around
I assume the phase needs to be considered as well not just the amplitude?

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Adam Taylor
Adam Taylor
11/17/2012 7:15:13 AM
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Re: One also has to look at the performance of the available Anti-Alias Filter and Buffer Amp
Excellent point the components supporitng the ADC/DAC and FPGA can often be the limiting factor in performance. Mixed signal design can be very tricky especially if you are using a wide band device. 

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JezmoSSL
JezmoSSL
11/17/2012 6:03:16 AM
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Re: Swap it around
yeah its all handled by one cyclone 3, the ADCs have calibration lookups, but the secret really is sophisticated ADC front ends.

The most complex part of the FPGA design in the routing of the audio data, complicated by the fact that you can change the sample rate on the fly and its possible to route an ADC input to a DAC output without it going out through the main serial data link, and you can gaurentee that its going to be dropped and kicked by roadies.

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SA_Penguin
SA_Penguin
11/16/2012 7:41:10 PM
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Re: Swap it around
Matched gains?  As in - insert a calibrated signal, and scale each result by a [different] mutiplication factor? If we are talking floating point math, 0.1dB precision, that's asking a fair bit of an ADC-based simple FPGA. Not that it can't be done, just the fact that you have 16 of the sods means a single, central FPGA would probably be easier.

Assuming audio ('Stage box' and 196K sample rate), the FPGA or CPLD in the ADC would be set as a simple low-pass, cutting off anything over 24.5KHz (1/8 sample rate). The central FPGA would become a multiple virtual graphic equalizer.

That would allow you to tweak the setup, each time the band moved to a different venue.

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JezmoSSL
JezmoSSL
11/15/2012 11:46:27 PM
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Re: Swap it around
at SSL the 'Stage box' I designed has 16 ADCs and 12 DACs running at 196K all run over a multiplexed 12 Mhz serial bus, which then gets mulitplexed into a 125Mhz serial bit stream which looks a lot like ethernet, so youve got a lot of high speed serial data wizzing about, and they get upset if the output/input stage gain is out by 0.1 dB, thats a design challenge !!!

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