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Tom Burke

Using Schematics to Capture a 'Hello World' App

Tom Burke
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shakeeb
shakeeb
2/9/2013 11:37:37 AM
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Beginner
Re: Even software developers...
"I always put a current limit on the power supply and wind it up till the expected current is drawn and the volts stabilise, look at the input levels and output levels with the scope and exercise with whatever signal source is appropriate."

 

That would definitely help to stop blowing up with excess or too less power.

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tomii
tomii
2/8/2013 7:50:57 PM
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Re: A beginners get home safe clause
I find, all to often, that thing not only not do what I want, but to add insult, they do exactly what I tell them to.

 

D'oh.

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jandecaluwe
jandecaluwe
2/8/2013 12:55:46 PM
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Re: A beginners get home safe clause
@Crusty "I want to use VHD but if I do not know how to get it to work in the way i want"

Is it possible to define clearly what you mean by "the way I want"? The problem may be a fundamental mismatch of expectations.

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Duane Benson
Duane Benson
2/8/2013 12:43:10 PM
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Re: A beginners get home safe clause
Crusty - one of the biggest (one of the very many) challenges I've had with learning Verilog is the tendency I have to think in terms of software. Had I been able to make some progress with the schematic entry first, I don't think I would have had so much of a problem thinking software.

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Duane Benson
Duane Benson
2/8/2013 12:36:05 PM
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Re: Even software developers...
Crusty - re: "a self blinking led that had got in the wrong tray in the components box DOH"

I've done something like that more times than I can count. :-)

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Crusty
Crusty
2/8/2013 5:26:06 AM
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A beginners get home safe clause
@Duane, Tomil: As a rank FPGA beginner the schematic was the only thing that worked first time for me.

60 years ago I started with the schematic translated to the PCB with descrete components. The next step to Software was hard but doable at the age of 30.

At 60 plus the HDL has been a very slow learning process, the Schematic capture stopped me binning the Papilio One as I got the same schematic as Tomil has used to work some time back.

I want to use VHD but if I do not know how to get it to work in the way i want, then I will use any method to get there, EVEN WIRING A MICRO TO THE OPERATIONAL BITS OF THE FPGA jsut to get where I want to be.

In the learning process like Duanes children and Dr Who just pushing and using everything helps.

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Crusty
Crusty
2/8/2013 5:12:08 AM
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Re: Even software developers...
@Duane What would be an analog equivalent to "hello world"? Is there such a thing?

I always put a current limit on the power supply and wind it up till the expected current is drawn and the volts stabilise, look at the input levels and output levels with the scope and exercise with whatever signal source is appropriate.

A Crusty Note of warning,  blinking a led, got caught last night.

One second blink test on divider chain on the FPGA board and led happily blinking, Trouble was it was a self blinking led that had got in the wrong tray in the components box DOH.

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JezmoSSL
JezmoSSL
2/7/2013 3:36:45 PM
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Blogger
Re: Schematics
Yeah I think we are going to move towards something of the sort, I made the mistake of looking in my predesessors desk today and found hundreds of blown antifuse devices, so i currently trying to decide what to make out of them, maybe some sort of sculpture.

I could even make a hat out of them for design west.

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rfindley
rfindley
2/7/2013 12:59:40 PM
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Re: Schematics
@Jezmo,

If you haven't yet looked at the Zynq security features, I think you will find them interesting.  Rather than securing your entire bitstream via anti-fuse, the Zynq has an eFuse register.  You can configure it to require secure (AES-encrypted) boot, and authenticate the bitstream against a set of fused keys in the part.  So, you can still support firmware updates without the risk of tampering (it also has tamper detection monitoring, at which point it erases the sram and stops functioning).

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hamster
hamster
2/7/2013 12:34:29 PM
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Blogger
Re: Schematics
In ISE, to view the HDL
  • Open the schematic
  • Expand "Design Utiltiies" in the process window
  • Double click on View HDL functional model

Scroll down till you find the "Architecture" matching the name of the schematic.

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