Hi. I'm new to All Programmable Planet, but chances are that you've seen some of my writings before.
I've been the editor-in-chief of EDN Magazine and the Microprocessor Report. I wrote my very first blog for the EDN Web site. It was called "Leibson's Law." For the last two and a half years I wrote the EDA360 Insider and Denali Memory Report blogs for Cadence, which -- as you are doubtless aware -- is one of the big three EDA vendors.
Now I'm about to start writing for All Programmable Planet, and this is my first post.
Max, the proprietor of All Programmable Planet, suggested that I write this first post to introduce myself. First and foremost I'm an engineer, although the first paragraph in this blog post is bound to mislead you. I've designed computers and workstations for the likes of HP and gone-and-forgotten EDA pioneer Cadnetix. (If it ain't on the Internet and if Mr. Google can't find it, it's forgotten.)
During those days of yore, I got a lot of experience in designing with one of the earliest forms of programmable logic -- the MMI PAL. Back then, we used a blow-and-go approach to programmable logic design and I had a pile of dead 16L8s that I kept on my workbench to prove my expertise.
By the way, here's a photo of my workbench at HP:
Sorry, I don't have a photo of the dead 16L8s.
Since those far-off times, programmable logic has made a few advancements; for example, FPGAs appeared on the scene.
I've spent the last decade working for companies that develop design tools and IP for ASIC and SoC development. I worked at Tensilica where I learned a lot about embedding 32-bit RISC processors into ASIC silicon. I then worked for Denali Software and Cadence, where I learned quite a bit more about ASIC-class IP and design tools for ASICs and SoCs.
Throughout this education, I observed that Moore's Law was taking ASICs and SoCs further and further out of reach of more and more design projects. Why? Because of the design costs. As Moore's Law has taken us from 180nm design rules at the beginning of the millennium to 28nm design rules today, ASIC and SoC design costs have risen from a few million dollars to several tens of millions of dollars because of the complexity of the resulting ICs. Those escalating costs mean that fewer and fewer systems can afford to make use of ASICs and SoCs because the sales volumes required to amortize design costs continue to climb.
So it might come as no surprise to you to learn that I now work at Xilinx. As ASIC design starts have been decreasing for more than a decade, the number of designs realized using programmable logic devices has risen significantly. This is also thanks to Moore's Law and the large number of resources now available on nanometer programmable silicon.
Programmable logic has changed a lot since my early design experiences with PALs. The first obvious change is that there's a lot more logic on one of today's FPGAs. There are also some really heavy-duty embedded blocks available, including DSP chunks, RAMs, and high-speed SerDes ports. The SerDes ports in particular are interesting in getting I/O rates up to multi-gigabit speeds per pin. That's sort of exciting all by itself -- and with the advent of serial-bus architectures such as PCIe -- the need for these SerDes ports is widespread.
For me, with my EDN/Microprocessor Report and Tensilica microprocessor background, one of the most significant new developments is the embedding of hard-core processors in programmable logic and the addition of software programmability to the FPGA's existing hardware programmability. That's something that's got me really excited. (And it's why I started this post with the quintessential "Hello World" C program, altered slightly for All Programmable Planet.)
I first started to write about this development nearly three years ago (see Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform -- Part 1
and Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform -- Case Studies -- Part 2
). I intuitively knew then that the Xilinx Zynq platform was going to make big changes to the way we design systems, and I've written about these developments several times in different blogs over the last three years.
Well, Xilinx Zynq All Programmable SoCs (as they're now called) have been shipping for more than a year, and that's one of the reasons that I jumped at the chance to join Xilinx more than five months ago. It's that big a deal, in my opinion.
I also jumped when Max gave me the chance to write a blog for All Programmable Planet. There are a lot of really interesting things happening at Xilinx right now -- things that will help you design better systems in a lot less time -- and I'm in the perfect place to tell you about those things in this blog.