Analog-to-digital (A/D) converters -- also known as ADCs -- are remarkably handy to have around for reading sensors and transducers, monitoring supply voltages, taking temperature readings, and the like.
They're especially handy if you've already got an A/D converter or two lurking in your design just waiting to be used. That's actually the case for all of the Xilinx 7 Series All Programmable FPGAs, 3D ICs, and SoCs. Each of these devices incorporates an AMS (analog mixed-signal) module called the XADC that includes two 12-bit, 1Msamples/sec A/D converters, a 16-channel analog multiplexer, and a second multiplexer connected to on-chip power supply voltages and an on-chip temperature sensor.
Here's a block diagram of the Xilinx 7 series XADC:
The two 12-bit, 1Msamples/sec A/D converters in the Xilinx XADC are good for a wide variety of industrial applications just as they are, but sometimes you need a bit more resolution... or perhaps two bits more.
Wouldn't you prefer to use what you've already got on chip rather than add BOM (bill of materials) cost and chew up board space with another component or two?
There is a way to obtain that additional A/D resolution if you're willing to give up sample rate. The technique is called "oversampling and decimation," and it's based on some solid fundamental principles starting with the Nyquist-Shannon sampling theorem, which gives the minimum sampling rate needed for a band-limited signal as follows:
fn = 2fm
Where fm is the maximum frequency of interest and fn is the sample rate.
Most engineers learn about the Nyquist sampling frequency somewhere along the line. Here it is, actually being useful.
Although it may not be intuitive, you can increase the effective number of bits (ENOB) of A/D resolution through a trick called oversampling gain, as described by the following equation:
fos = 4W · fs
Where fos is the oversampling frequency that you need to achieve W bits of additional resolution compared to what you have at sample rate fs.
How is this possible? It sort of looks like magic, doesn't it?
Well, like most magic tricks, this one requires the proper preparation. Here are the rules:
The band-limited signal being measured must not vary by more than 0.5 LSB (least-significant bit) during a conversion over the entire 1/fs period. (Note: NOT 1/ fos)
There needs to be at least 1 LSB of Gaussian (white) noise with a mean value of zero present on the signal being measured.
The first rule is pretty obvious. If the signal being measured varies more than 0.5 LSB within the sample period, then you're not really conforming to the Nyquist-Shannon rules, and so the assumptions being made here are invalid. The second rule looks pretty sketchy, doesn't it? Since when did you actually welcome noise in a system?
Let's look at how this all works to see why we need the noise -- then we'll discuss the noise sources.
I will have to use "it's better late than never" excuse here.
I had quite a bit of training in analog signal processing theory, but very little in DSP theory. However, I learned as a consumer to have profound admiration for the breakthroughs of DSP such as the incredible compression of information in a single old fashion analog voice channel. The technique used in this article is very interesting and mind boggling enough to arouse the interest of any motivated electrical engineering student - even the older ones as me. I will try to make time to dig more into this concept.
Now, the excuse. The reasons I chipped in so late is I was referred to this blog by David Ashton in the discussion going on in the most recent blog launched this past Thursday by Terry Ashton on DNL in ADCs.
Hamster: Adding noise reminds me of ring laser gyros. They have really good resolution, but can "lock in" if they stand still. to avoid this thay are constantly shaken.
I wish I could oversample my memory and retrieve lost bits...
In my past work, we dealt with our ADC's a different way, as the signal was only existant for a short period of time (which was, fortunately, deterministic) - so we got exactly one (!) sample of the data every time. (maybe 2, depending on how you define it). This required us to build very high-precision front-ends. The place I worked for buit ome of the best ADCs available *anywhere* for the environment - in the 90's, the foundry was popping out true 12b ADCs that operated at ~4MHz, with INL and DNL of 1.0 (at ~50% yield). That's a mean feat, even by today's standards.
Because of the way the sensor that provided the analog signal works, we could use the sensor itself to integrate the signal, because the PSD of the noise function was Gaussian in nature.
But this is perfectly applicable to doing similar things at the ADC. You can use the ADC to integrate out the noise, too... It's all about increasing your SNR, and that can be done in either the analog or digital domain - although you pay a bigger penalty in the digital domain (depending on your world view).
So, if there is *NO* noise, there can be no gain in the SNR, and therefor no advantage in oversampling. If your signal were pure, and you added noise in, I don't believe you're doing yourself any favors, but I don't know the math behind all that any more (it's been years since I've worked it out). I would aslo tend to think that by using an LFSR to add noise to the system, that you would be adding a lot of noise that is periodic (and therefore not Gaussian) due to the edges in the transitions. Maybe that spreads out with bandwidht or depth of the LFSR, but I dunno. But by the same token clock noise on your signal is periodic, and not Gaussian, so is very likely to remain in your final signal, unless you can manage to sample away from thos edge transitions and their propagation effects. That's not easy, especially since theyre usually ringing.
If you *do* have noise in the system (and if notihng else, the ADC's QSE guarantees the LSB is usually noisy), then you can gain a few extra bits there.
To gain SNR through oversampling, you get an improvement of sqrt(N), where N is the number of samples. That is, if you sample twice, you get an SNR improvement of sqrt(2). If you sample 4x, you get an SNR improvement of 2. Oh, those are multiplicative. By integrating in the analog domain, you are not adding ADC noise in your samples, and you can ensure that the LSB of your ADC is far down "in the noise." If you are doing the integration in the digital domain, then the ADC noise becomes one of the components that is lowering your SNR. (Basically, in the analog domain, we put as much gain as we possibly can right up front, so the net effect of all following components impact on SNR is small by comparison - this is why the LNA in a radio receiver sets the noise floor for the system).
Regardless, there's not usually much point in sampling at more than about 1/2 your SNR (that is, if you have an SNR of 128, there's not really much more than 8 bits of data there). The only reason we ever really would sample at a deeper resolution than that is to "smooth" the data, but the rule of thumb we always used was to sample at 1/2 SNR.
Now one of the things I find reallyinteresting today is the intentional undersampling of carriers to create software defined radios (SDR). Turns out that you don't need to sample at fN of the carrier, but only at the fN of the information. It requires good front-end filters because of the aliasing, but I find it to be really neato! And it makes the whole analog front end (AFE) easier. And ADCs easier to find.
@Steve: thank you very much for your explanation. I was trying to make up my mind about your blog with a thought-experiment in the limit...
The maths behind using gaussian noise for increasing resolutions seems harsh. I'm used to use oversampling and other techniques for noise suppression and conformation, but I'd never thought about using noise in this way.
¿Noise as a good thing? This blog is very inspiring and thought provoking!!!
Steve Leibson 2/28/2013 10:38:22 PM User Rank Blogger
Re: So *that's* how it works!
@Warren: It would be tough to use the on-chip 12-bit A/D converters when you're talking about noise that's on the order of 1 LSB. You need more resolution than that. Fortunately, you need do this at design time, not during run time so you can use a DSO and some spectrum analysis to verify the Gaussian noise distribution and zero dc offset..
Steve Leibson 2/28/2013 10:33:20 PM User Rank Blogger
Re: Bringing it to the limit
@Garcia-Lasheras: As Max has already pointed out, there are 1-bit A/D converters although they don't use this particular technique. Say you want 12 bits of resolution from a 1-bit converter. You need 4^11 samples to extend the resolution. That's 2^12 samples or 4096 samples per oversample. For a 1KHz signal, you need a 4Msamples/sec converter.
There are easier ways to digitize a signal and I'm afraid you're really beyond the law of diminishing returns long before this. I'd not try to extend an A/D converter's range by more than two bits with this technique, based on what I've read. In true digital engineer's form, I'm using the approximations of the actual math so I know there be monsters lurking if I violate the rules associated with those assumptions. In other words, I'd have to understand the math better.
If you're a seasoned FPGA user, you know that one of the real savings in system development time is the time you gain by not needing to do the physical design of a nanometer IC.
Luke Miller was not always an HLS advocate. It seems he had some bad experiences with an earlier tool. "My heart was all walled up and needed counseling." Fortunately, he's getting useful work out of the Xilinx Vivado HLS tool.
The secret of using the Xilinx Zynq SoC to quickly develop systems is to use the ARM processors to execute code; find code that needs further acceleration through profiling; then configure part of the FPGA fabric as an accelerator and couple it to the executing code.
The latest EEVblog video from Dave Jones compares the Rigol DS1052E digital sampling oscilloscope against the company's latest low-cost DSO, the DS2072.
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